Patents by Inventor Brian Arsenault

Brian Arsenault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9604371
    Abstract: Interlocking knives are provided. The interlocking knives include at least a first knife and a second knife. The first knife includes a blade and a handle. At least one slot may be formed through the blade of the first knife. The second knife also includes a blade and a handle. The second knife includes at least one slot. The at least one slot of the second knife interlocks with the at least one slot on the first knife. A swivel plate may be pivotally connected to the first knife. The swivel plate is operable to pivot towards the second knife into a locked position, securing the second knife to the first knife.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: March 28, 2017
    Inventors: Michael Matthews, Brian Arsenault
  • Publication number: 20160354937
    Abstract: Interlocking knives are provided. The interlocking knives include at least a first knife and a second knife. The first knife includes a blade and a handle. At least one slot may be formed through the blade of the first knife. The second knife also includes a blade and a handle. The second knife includes at least one slot. The at least one slot of the second knife interlocks with the at least one slot on the first knife. A swivel plate may be pivotally connected to the first knife. The swivel plate is operable to pivot towards the second knife into a locked position, securing the second knife to the first knife.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 8, 2016
    Inventors: Michael Matthews, Brian Arsenault
  • Patent number: 8806123
    Abstract: A data storage system having a plurality of disk drive sections, each one of the disk drive sections having a plurality of disk drives. Each one of a plurality of secondary SAS expanders is coupled to a corresponding one of the disk drive sections. Each one of the secondary SAS expanders has: (1) a plurality of first ports each one being connected to a corresponding one of the disk drives in the corresponding one of the plurality of disk drive sections coupled thereto; and (2) a second port. A main SAS expander has: (1) a first port; and (2) N second ports, each one of the N second ports of the main expander being connected to the second port of a corresponding one of the plurality of N secondary expanders. A storage processor is coupled to the second port of the main SAS expander.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 12, 2014
    Assignee: EMC Corporation
    Inventors: Brian Daniel Kennedy, Brian Arsenault, William F. Baxter, III, Antonio Fontes
  • Patent number: 6587957
    Abstract: A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 1, 2003
    Assignee: EMC Corporation
    Inventors: Brian Arsenault, Victor W. Tung, Rudy M. Bauer
  • Patent number: 6539492
    Abstract: A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: March 25, 2003
    Assignee: EMC Corporation
    Inventors: Brian Arsenault, Victor W. Tung, Rudy M. Bauer
  • Patent number: 6493795
    Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: December 10, 2002
    Assignee: EMC Corporation
    Inventors: Brian Arsenault, Victor W. Tung, Jeffrey Stoddard Kinne
  • Patent number: 6360319
    Abstract: A method and a control device is provided for upgrading computer system hardware, for example, on a printed circuit board, with system revision information. The method includes receiving, a serial data stream having data bits associated with the system revision information through a serial input of the control device, determining the start of the data bits, and storing at least a portion of the data bits associated with the system revision information within a read-only register of the control device.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: March 19, 2002
    Assignee: EMC Corporation
    Inventors: Brian Arsenault, Victor W. Tung