Abstract: A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).

Abstract: A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

Abstract: A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.

Abstract: A technique comprising: forming a first conductor pattern at least partly defining source and/or drain conductors for one or more thin film transistor devices; exposing the conductor pattern to a reactive halogen species; and depositing organic semiconductor channel material directly over the exposed first conductor pattern to provide one or more semiconductor channels between source and drain conductors of the exposed first conductor pattern.

Abstract: Method for forming an organic polymer insulator over a first conductor pattern defining a first level of conductors for a thin-film transistor device. A first conductor layer is formed over the organic polymer insulator and a second conductor layer formed over the first conductor layer. The second conductor layer is patterned to define a second level of conductors by exposing the second conductor layer to liquid etchant in selected regions to form a second conductor pattern. The first conductor layer may be located in the selected regions and the first conductor layer and the organic polymer insulator may comprise surface materials that exhibit a substantially zero etch rate for the liquid etchant. The first conductor layer may be less permeable to the liquid etchant than the organic polymer insulator and/or more resistant to damage by the liquid etchant than the organic polymer insulator may be patterned.

Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).

Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.

Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.