Abstract: Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.

Abstract: The disclosed implementations allow automatic and transparent creation of data relationships in a database application or other application in response to user generated trigger events. Related data records can be stored and displayed in layouts, screens, forms and user interfaces provided by the database application or other application. Additional or extended information corresponding to the related data can be stored and displayed.

Abstract: A compound field is automatically created in response to a trigger event. In one aspect, a user selects a field type and a compound field associated with the field type is automatically created. A compound field can be manipulated and presented as a single conceptual unit in a user interface (e.g., a form, screen or layout) of an application (e.g., a database application). When an object representing the compound field is dragged and dropped or otherwise selected in the user interface, the compound field is expanded to reveal one or more subfields capable of receiving data from a user. In another aspect, one or more background tables are automatically and transparently created to store compound field objects. In another aspect, a user can create their own compound field types.

Abstract: The disclosed implementations allow automatic and transparent creation of data relationships in a database application or other application in response to user generated trigger events. Related data records can be stored and displayed in layouts, screens, forms and user interfaces provided by the database application or other application. Additional or extended information corresponding to the related data can be stored and displayed.

Abstract: A method, an apparatus, and a computer program are provided for managing commands in a multi-queue system. Depending on the types of queues that are utilizes, there can be difficulties in managing the order of execution of commands. To alleviate this problem, dependencies and identifiers are associated with each command that allow command queues in the entire multi-queue system to monitor the status of all commands.

Abstract: An apparatus, a method, and a computer program are provided for stalling the performance of commands. In a normal performance system, there are multiple steps that have to be complete for a command to be performed. However, commands may not be performed for a variety of reasons. Typically, a system will utilize a flush mechanism to alleviate a buildup of commands that have not been performed. Flushing, though, can be costly. Therefore, a more efficient system of stalling the performance of commands has been developed to alleviate the problem of missed command performance and the problems associated with system flushes.

Abstract: A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

Abstract: A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

Abstract: Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: A system and method for determining whether to retire a data entry from a buffer. A portion of the retirement conditions is processed prior to the data entry being considered for retirement resulting in faster processing of remaining retirement conditions at the time retirement of the data is to be considered. The results from the pre-processing are stored as predecoded retirement information, which is later used with the remaining retirement conditions to determine whether the data is to be retired from the buffer.

Abstract: The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

Abstract: The present invention provides for a system for allocating resources in a multiprocessor environment. Blocking logic is configured to receive at least a request for resources from a device and to block repeat requests from the device. A first arbiter is coupled to the blocking logic and configured to receive a request for resources and a tag uniquely identifying the device, to perform a first arbitration, and to transmit the request and the tag to a first requester, based on the first arbitration. The first requestor is coupled to the first arbiter and configured to receive a request for resources and a tag from the first arbiter, to transmit the request and the tag to a second arbiter, and to receive a first grant signal from the second arbiter.

Abstract: The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and hold their requests for two full-speed cycles. The arbitration method gives priority to the requests from the low-priority requesters and guarantees that two requests made by the half-speed requestors at the beginning of a low-speed cycle will be granted over the course of the low-speed cycle. The requests generated by the low-speed requestors are issued in phases. Issuance of later phases of a request is blocked when the request has been granted in an earlier phase.

Abstract: An apparatus, a method, and a computer program are provided for stalling the performance of commands. In a normal performance system, there are multiple steps that have to be complete for a command to be performed. However, commands may not be performed for a variety of reasons. Typically, a system will utilize a flush mechanism to alleviate a buildup of commands that have not been performed. Flushing, though, can be costly. Therefore, a more efficient system of stalling the performance of commands has been developed to alleviate the problem of missed command performance and the problems associated with system flushes.

Abstract: A method, an apparatus, and a computer program are provided for managing commands in a multi-queue system. Depending on the types of queues that are utilizes, there can be difficulties in managing the order of execution of commands. To alleviate this problem, dependencies and identifiers are associated with each command that allow command queues in the entire multi-queue system to monitor the status of all commands.