Patents by Inventor Brian Bernier

Brian Bernier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325836
    Abstract: An integrated circuit with transmission line error detection comprises a substrate, a package enclosing the substrate, a lead extending from the inside of the package to the outside of the package, and a circuit supported by the substrate. The circuit includes an input circuit and an output circuit. A first wire is coupled between the output circuit and the lead and a second wire is coupled between the lead and the input circuit so that the input circuit receives a signal generated by the output circuit after the signal has been transmitted across the first and second wires.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 18, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Nicolas Rigoni, Juan Manuel Cesaretti, Brian Bernier
  • Publication number: 20070162956
    Abstract: A system to prevent unauthorized access to a protected device includes a test access port operable to mate with a test access connector, a security key port operable to mate with a security key and a security device in electrical communication with the test access port and the security key port. The protected device is in electrical communication with the test access port when the security device is enabled based on the security key. The test equipment is authorized for access to the protected device when the security device is enabled.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 12, 2007
    Applicant: Honeywell International Inc.
    Inventors: James Tucker, Brian Bernier
  • Publication number: 20070086257
    Abstract: A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Applicant: Honeywell International Inc.
    Inventors: Brian Bernier, Jason Waltuch
  • Publication number: 20070044158
    Abstract: In one embodiment, a system comprises debug functionality, a debug interface communicatively coupled to the debug functionality, and a hardware key interface. Communication with the debug functionality over the debug interface is not permitted if an authorized hardware key is not communicatively coupled to the hardware key interface.
    Type: Application
    Filed: November 4, 2005
    Publication date: February 22, 2007
    Applicant: Honeywell International Inc.
    Inventors: Edwin Cruzado, William Dalzell, Brian Bernier
  • Publication number: 20060242696
    Abstract: In one embodiment, a system comprises application-specific functionality, anti-tamper functionality to detect an unauthorized attempt to interact with the application-specific functionality; and a hardware key interface to communicatively couple the system to a hardware key. An attempt to interact with the application-specific functionality is considered unauthorized if an authorized hardware key is not communicatively coupled to the hardware key interface when the attempt occurs.
    Type: Application
    Filed: November 4, 2005
    Publication date: October 26, 2006
    Applicant: Honeywell International Inc.
    Inventors: Edwin Cruzado, William Dalzell, Brian Bernier
  • Publication number: 20060242465
    Abstract: In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line. The system further comprises a debug interface to communicatively couple the system to a debug device external to the system. The debug interface comprises a transmit (TX) line, receive (RX) line, and a clock (CLK) line. The system transmits data output by the JTAG functionality on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG functionality on the TDO line, TR line and the TMS line.
    Type: Application
    Filed: November 4, 2005
    Publication date: October 26, 2006
    Applicant: Honeywell International Inc.
    Inventors: Edwin Cruzado, William Dalzell, Brian Bernier