Patents by Inventor Brian Boles
Brian Boles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7650440Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.Type: GrantFiled: April 17, 2007Date of Patent: January 19, 2010Assignee: Microchip Technology IncorporatedInventors: Steven Dawson, Willem Smit, Maria Smit, legal representative, Brian Boles
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Patent number: 7634596Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.Type: GrantFiled: March 15, 2007Date of Patent: December 15, 2009Assignee: Microchip Technology IncorporatedInventors: Igor Wojewoda, Brian Boles, Steve Bradley, Gaurang Kavaiya
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Patent number: 7603601Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.Type: GrantFiled: February 16, 2006Date of Patent: October 13, 2009Assignee: Microchip Technology IncorporatedInventors: Cristian P. Masgras, Michael Pyska, Edward Brian Boles, Joseph W. Triece, Igor Wojewoda, Mei-Ling Chen
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Publication number: 20080028110Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.Type: ApplicationFiled: April 17, 2007Publication date: January 31, 2008Inventors: Steven Dawson, Willem Smit, Maria Smit, Brian Boles
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Publication number: 20070283052Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.Type: ApplicationFiled: March 15, 2007Publication date: December 6, 2007Inventors: Igor Wojewoda, Brian Boles, Steve Bradley, Gaurang Kavaiya
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Patent number: 7206924Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.Type: GrantFiled: December 31, 2003Date of Patent: April 17, 2007Assignee: Microchip Technology Inc.Inventors: Edward Brian Boles, Rodney Drake, Darrel Johansen, Sumit Mitra, Joseph Triece, Randy Yach
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Patent number: 7203818Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.Type: GrantFiled: March 9, 2004Date of Patent: April 10, 2007Assignee: Microchip Technology Inc.Inventors: Edward Brian Boles, Rodney Jay Drake, Darrel Ray Johansen, Sumit K. Mitra, Randy Yach, James Grosbach, Joshua M. Conner, Joseph W. Triece
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Patent number: 6985986Abstract: A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.Type: GrantFiled: June 1, 2001Date of Patent: January 10, 2006Assignee: Microchip Technology IncorporatedInventors: Brian Boles, Joseph W. Triece, Joshua M. Conner
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Publication number: 20050257016Abstract: A controller offers various security modes for protecting program code and data stored in memory and ensuring that the protection is effective during all normal operating conditions of the controller. The controller includes configuration settings that segment program memory into a boot segment, a secure segment and a general segment, each with a particular level of security including no enhanced protection. The boot code segment (BS) is the most secure and may be used to store a secure boot loader. The secure code segment (SS) is useful for storing proprietary algorithms from third parties, such as algorithms for separating ambient noise from speech in speech recognition applications. The general code segment (GS) has the least security. The controller is configured to prevent program flow changes that would result in program code stored in high security segments from being accessed by program code stored in lower security segments.Type: ApplicationFiled: May 17, 2004Publication date: November 17, 2005Inventors: Brian Boles, Sumit Mitra, Steven Marsh
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Publication number: 20040177211Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.Type: ApplicationFiled: March 9, 2004Publication date: September 9, 2004Applicant: Microchip Technology IncorporatedInventors: Edward Brian Boles, Rodney Jay Drake, Darrel Ray Johansen, Sumit K. Mitra, Randy Yach, James Grosbach, Joshua M. Conner, Joseph W. Triece
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Publication number: 20040158692Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behaviour of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.Type: ApplicationFiled: December 31, 2003Publication date: August 12, 2004Applicant: Microchip Technology IncorporatedInventors: Edward Brian Boles, Rodney Drake, Darrel Johansen, Sumit Mitra, Joseph Triece, Randy Yach
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Patent number: 6708268Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.Type: GrantFiled: March 26, 1999Date of Patent: March 16, 2004Assignee: Microchip Technology IncorporatedInventors: Edward Brian Boles, Rodney Drake, Darrel Johansen, Sumit Mitra, Joseph Triece, Randy Yach
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Publication number: 20040021483Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.Type: ApplicationFiled: April 21, 2003Publication date: February 5, 2004Inventors: Brian Boles, Richard Fischer, Sumit Mitra, Rodney Drake, Steven A. Bowling, Bryan Kris, Steven Marsh, Hassan Harb
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Patent number: 6552567Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.Type: GrantFiled: September 28, 2001Date of Patent: April 22, 2003Assignee: Microchip Technology IncorporatedInventors: Brian Boles, Richard Fischer, Sumit Mitra, Rodney Drake, Stephen A. Bowling, Bryan Kris, Steven Marsh, Hassan Harb
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Publication number: 20030061464Abstract: An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.Type: ApplicationFiled: June 1, 2001Publication date: March 27, 2003Inventors: Michael I. Catherwood, Brian Boles, Stephen A. Bowling, Joshua M. Conner, Rodney Drake, John Elliot, Brian Neil Fall, James H. Grosbach, Tracy Ann Kuhrt, Guy McCarthy, Manuel Muro, Michael Pyska, Joseph W. Triece
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Publication number: 20030005269Abstract: A processor configuration for processing multi-precision shift instructions is provided. The multi-precision shift instructions are executed following a previous shift instruction of the same increment, such as a logical or arithmetic left or right shift operation. The first shift instruction shifts a first memory word by the shift increment and stores this shifted value into memory. The second, and any subsequent, multi-precision shift instruction shifts the next memory word by the shift increment and concatenates the bits shifted out of the previously shifted memory word into bit positions of the memory word presently being shifted. This concatenated value is then stored back to memory and forms another part of the multi-precision shifted value.Type: ApplicationFiled: June 1, 2001Publication date: January 2, 2003Inventors: Joshua M. Conner, John Elliot, Michael I. Catherwood, Brian Neil Fall, Brian Boles
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Publication number: 20020188830Abstract: Bit value transfer operation instructions are provided. The bit value transfer operation instructions themselves include four instructions, each for selecting a bit value contained in a source bit position of a data memory location and writes the bit value to a destination bit position of another data memory location. Moreover, the instructions specify a source bit position of a data memory location containing a bit value to select, a destination bit position of another data memory location to write the bit value, and the data memory location of an operand from which to read or write the bit value. Processing a bit value transfer operation instruction includes fetching and decoding a bit value transfer instruction. The method further includes executing the bit value transfer instruction on a source bit position of a first data memory location to select a bit value in the source bit position of the first data memory location.Type: ApplicationFiled: June 1, 2001Publication date: December 12, 2002Inventors: Brian Boles, Michael Catherwood
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Publication number: 20020188784Abstract: A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.Type: ApplicationFiled: June 1, 2001Publication date: December 12, 2002Inventors: Brian Boles, Joseph W. Triece, Joshua M. Conner
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Publication number: 20020180627Abstract: A method and A/D module for automatically triggering analog to digital sampling and conversion are provided. The A/D module selects various analog signals for input. Up to four of the selected signals are sampled due to the initiation of a sampling operation. The A/D periodically polls for a heartbeat condition. Upon the occurrence of the heartbeat condition the sampling is ended and a conversion sequence is automatically started to convert the selected signals to binary representations. When the conversion sequence is completed the binary representation is stored to memory and sampling sequence is automatically started.Type: ApplicationFiled: June 1, 2001Publication date: December 5, 2002Inventor: Brian Boles
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Patent number: 6339413Abstract: A device including a microcontroller fabricated on a semiconductor chip is used to control an LCD display of an external system intended to be controlled by the microcontroller. The microcontroller enters a sleep state in which it operates in a battery power conservation mode during periods of time when functional activity of the microcontroller is reduced. The microcontroller awakens from the sleep state for resumption of activity when such a period ends. Timing to the LCD is decoupled from the microcontroller's own internal clock when the independent internal on-chip clock, which may be an RC oscillator, is selected by the user of the device. This allows the chip to continue to drive the LCD display even though the microcontroller's internal clock has stopped during the sleep.Type: GrantFiled: June 28, 1996Date of Patent: January 15, 2002Assignee: Microchip Technology IncorporatedInventors: Rodney Drake, Brian Boles