Abstract: An apparatus may include a pipeline circuit configured to process packets and an authentication engine configured to authenticate packets and to provide an authentication signal to the pipeline circuit based on whether packets have been authenticated. The apparatus may further include a control circuit configured to route a given incoming packet to both the authentication engine and to a bypass path. The bypass path may be configured to provide a copy of the given incoming packet to the pipeline circuit to bypass the authentication engine.

Abstract: Examples of the present disclosure relate generally to implementing higher-layer processing on time-sensitive data blocks at a physical-layer-interface device. Some examples include logic to perform operations, the operations including providing data blocks to a physical-layer-interface device. The operations may also include adding dummy data into one or more time-sensitive data blocks of the data blocks being provided to the physical-layer-interface device. A size of the dummy data corresponding to a size of higher-layer-processing data. Other example operations may include removing higher-layer-processing data from a first ingressing data block. The other operations may also include removing a portion of the first ingressing data block and adding the portion to a subsequent ingressing data block. A size of the portion corresponding to the size of integrity-detection data. The other operations may also include removing the integrity-detection data from an ingressing data block.

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Abstract: An apparatus may include a pipeline circuit configured to process packets and an authentication engine configured to authenticate packets and to provide an authentication signal to the pipeline circuit based on whether packets have been authenticated. The apparatus may further include a control circuit configured to route a given incoming packet to both the authentication engine and to a bypass path. The bypass path may be configured to provide a copy of the given incoming packet to the pipeline circuit to bypass the authentication engine.

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Abstract: A PHY constituted of: a clock arranged to generate a time signal indicative of the current time; and an egress stamp functionality arranged to: receive a data packet on the egress side, extract data from a predetermined section of the received data packet, and responsive to the extracted data, perform one of a plurality of predetermined timestamp operations, the plurality of predetermined timestamp operations comprising: generating a timestamp signal responsive to the generated time signal; not generating a timestamp signal; or modifying a timestamp written in the received data packet.

Abstract: A PHY constituted of: a clock arranged to generate a time signal indicative of the current time; and an egress stamp functionality arranged to: receive a data packet on the egress side, extract data from a predetermined section of the received data packet, and responsive to the extracted data, perform one of a plurality of predetermined timestamp operations, the plurality of predetermined timestamp operations comprising: generating a timestamp signal responsive to the generated time signal; not generating a timestamp signal; or modifying a timestamp written in the received data packet.

Abstract: Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.

Abstract: A physical layer device provides both timestamp processing and security processing. The timestamp processing may be PTP processing according to IEEE Std. 1588 and/or OAM processing according to ITU-T Recommendation Y.1731. The security processing may be MACsec processing according to IEEE Std. 802.1AE. The timestamp processing may delay some packets to avoid impairing accuracy of timing information. For example, the accuracy of timing information could be impaired when a packet containing the timing information is delay due to additional bits added to a preceding packet to include a security tag and integrity check value.

Abstract: A physical layer device provides security processing on communication frames that may include tags or headers that are for use in a wide area network. As frames pass through the physical layer device, the frames are classified for a type of security processing. Depending on the classification a cipher is applied to the frames for integrity checking of data in the frames. Some frames are also encrypted. The security processing may exclude some of the tags or headers. The frames may also be filtered and buffered.

Abstract: Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.

Abstract: Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.

Abstract: Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.

Abstract: A system handles timing information within a packet-switched network. The system classifies packets for processing depending on the packet type. After classification, a new timestamp value may be produced depending on the packet classification. The new timestamp value may use a timestamp value from the received packet, a value from a local clock, and an offset value. The timestamp value may be written into the packet, depending on the packet classification, and checksum-type fields may additionally be updated in the packet. In some embodiments, multiple physical layer circuits are integrated with a local clock circuit.

Abstract: A physical layer device provides both timestamp processing and security processing. The timestamp processing may be PTP processing according to IEEE Std. 1588 and/or OAM processing according to ITU-T Recommendation Y.1731. The security processing may be MACsec processing according to IEEE Std. 802.1AE. The timestamp processing may delay some packets to avoid impairing accuracy of timing information. For example, the accuracy of timing information could be impaired when a packet containing the timing information is delay due to additional bits added to a preceding packet to include a security tag and integrity check value.

Abstract: A physical layer device provides security processing on communication frames that may include tags or headers that are for use in a wide area network. As frames pass through the physical layer device, the frames are classified for a type of security processing. Depending on the classification a cipher is applied to the frames for integrity checking of data in the frames. Some frames are also encrypted. The security processing may exclude some of the tags or headers. The frames may also be filtered and buffered.

Abstract: A system handles timing information within a packet-switched network. The system classifies packets for processing depending on the packet type. After classification, a new timestamp value may be produced depending on the packet classification. The new timestamp value may use a timestamp value from the received packet, a value from a local clock, and an offset value. The timestamp value may be written into the packet, depending on the packet classification, and checksum-type fields may additionally be updated in the packet. In some embodiments, multiple physical layer circuits are integrated with a local clock circuit.

Abstract: The present invention provides a method and apparatus for improving transmission of control information within a network device and between multiple connected network devices. Specifically, a control path is included within a network device that is independent of the data path and dedicates control path resources to each distributed processor within the network device. Dedicating resources insures that each processor has sufficient bandwidth on the control plane to transmit control information at high frequencies. This may prevent starvation of data transmissions during periods of high control information transfers and may also reduce the likelihood or further spreading of control information storms when one or more network devices in a network experiences a failure.

Abstract: The present invention provides a method and apparatus for authenticating the identities of network devices within a telecommunications network. In particular, multiple identifiers associated with a network device are retrieved from and used to identify the network device. Use of multiple identifiers provides fault tolerance and supports full modularity of hardware within a network device. Authenticating the identity of a network device through multiple identifiers allows for the possibility that hardware associated with one or more of the identifiers may be removed from the network device. For example, a network device may still be automatically authenticated even if more than one card within the device are removed as long as at least one card corresponding to an identifier being used for authentication is within the device during authentication.

Abstract: The present invention provides an upper layer network device with one or more physical layer data test ports. The data supplied to the test ports reflects the data received by the network device with minimal modification and no upper layer translation or processing, and supplying the data to the test ports does not impact or disrupt the service provided by the network device. Only a small portion of the network device need be operable to send data to the test ports. In addition, the test ports are programmable while the network device is operating and without impacting its operation. Moreover, because the test ports are programmable—that is, they are not dedicated—they may be re-programmed for normal device operation.