Abstract: There is provided an x-ray detector having a number of x-ray detector sub-modules. Each detector sub-module is an edge-on detector sub-module having an array of detector elements extending in at least two directions, wherein one of the directions has a component in the direction of incoming x-rays. The detector sub-modules are stacked one after the other and/or arranged side-by-side. For at least part of the detector sub-modules, the detector sub-modules are arranged for providing a gap between adjacent detector sub-modules, where at least part of the gap is not directed linearly towards the x-ray focal point of an x-ray source.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: There is provided an x-ray detector having a number of x-ray detector sub-modules. Each detector sub-module is an edge-on detector sub-module having an array of detector elements extending in at least two directions, wherein one of the directions has a component in the direction of incoming x-rays. The detector sub-modules are stacked one after the other and/or arranged side-by-side. For at least part of the detector sub-modules, the detector sub-modules are arranged for providing a gap between adjacent detector sub-modules, where at least part of the gap is not directed linearly towards the x-ray focal point of an x-ray source.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: A system and method is provided for input and output between networked hardware components. The system can convert hardware control signals into network frames for transmission over a network fabric. Meta-data or data payload information may also be transmitted. The system can then receive network frames and convert them into replicated hardware control signals for execution. Multiple hardware components can work together for execution of coordinated actions.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.