Abstract: The present invention relates to methods of treating, preventing, and/or improving disorders and conditions related to certain metabolic abnormalities including methods of improving blood lipid profiles and muscle recovery and repair in athletes, methods of treating fibromyalgia, erectile dysfunction, diseases associated with certain HLA-DQ gene alleles and/or gluten intolerance, including Celiac Disease, headaches and migraines, as well as idiopathic neuropathy, inability to sleep, inability to concentrate, and/or neurological development issues in children, the methods involving the administration of one or more downstream folate compounds and optionally methyl-B12. In one particular embodiment, the method comprises administration of L-methylfolate. In certain embodiments, the method further involves identifying a subject organism with a malfunction in one or more of the folate or B4 cycles. In certain embodiments, such a malfunction is one or more of the C677T and A1298C genetic polymorphisms.

Abstract: A phase-locked-loop (PLL) is presented. An embodiment of the PLL includes an analog-to-digital converter (ADC) receiving and digitizing a signal from a crystal oscillator; a digital circuit processing the digitized signal from the ADC in comparison with an output signal of the PLL to provide control signals; and a digitally-controlled oscillator providing the output signal in response to the control signals from the digital circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Abstract: A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC) signal during an active mode of operation. The phase correction circuit further generates an FD output signal in response to the periodic MMD output signal and a preliminary multi-bit phase correction control (PPCC) signal during a calibration mode of operation. A control circuit is provided, which generates the modulus control signal, the PPCC signal and the CPCC signal during the active mode of operation.

Abstract: A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a second current carrying terminal electrically coupled to the input of the ADC. The impedance element can include a resistor and a capacitor, which are electrically connected in parallel. A gain device, such as a programmable multiplier, may also be provided, which has an input responsive to the signal generated at the output of the ADC and an output electrically coupled to the input of the DAC.

Abstract: A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.

Abstract: An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to shift a dynamic range of the control output of the control circuit with respect to a dynamic range of the control input of the PLL circuit. The apparatus may be implemented with an oscillator, such as a MEMs oscillator, in a single chip.

Abstract: Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

Abstract: The present invention relates to methods of treating, preventing, and/or improving disorders and conditions related to certain metabolic abnormalities including methods of improving blood lipid profiles and muscle recovery and repair in athletes, methods of treating fibromyalgia, erectile dysfunction, diseases associated with certain HLA-DQ gene alleles and/or gluten intolerance, including Celiac Disease, headaches and migraines, as well as idiopathic neuropathy, inability to sleep, inability to concentrate, and/or neurological development issues in children, the methods involving the administration of one or more downstream folate compounds and optionally methyl-B12. In one particular embodiment, the method comprises administration of L-methylfolate. In certain embodiments, the method further involves identifying a subject organism with a malfunction in one or more of the folate or B4 cycles. In certain embodiments, such a malfunction is one or more of the C677T and A1298C genetic polymorphisms.

Abstract: A voltage controller oscillator (VCO) circuit is provided for use in a phase-locked loop (PLL) circuit. The VCO circuit has a VCO and a low pass filter. The VCO includes a first input that receives a first voltage control signal from an output of a PLL circuit loop filter, a second input that receives a second voltage control signal, and an output that provides a periodic output signal. The low-pass filter includes an input connected to the output of the PLL circuit loop filter, and an output connected to the second input of the VCO. The first input of the VCO provides high frequency voltage control, and the second input of the VCO provides low frequency voltage control.

Abstract: An extended range voltage controller oscillator (VCO) circuit for use in a phase-locked loop (PLL) circuit is provided. The VCO circuit includes two additional pairs of varactors which are used to extend the range of the VCO circuit around its center frequency.