Patents by Inventor Brian Butcher

Brian Butcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210091715
    Abstract: A solar panel assembly includes a substrate and a solar array coupled to the substrate. The solar array includes a plurality of photovoltaic cells. An optical layer is disposed over the solar array. The optical layer, the solar array, and the substrate together form a solar assembly. A frame surrounds the solar assembly and includes a plurality of frame members. Each frame member of the plurality of frame members includes an arcuate member that forms an aerodynamic outer edge of the frame member.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 25, 2021
    Applicant: ZampTech Sub LLC
    Inventors: Conor Miller, Brian Butcher
  • Patent number: 9425394
    Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 23, 2016
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Brian Butcher, Randall J. Higuchi, Yun Wang
  • Publication number: 20150093876
    Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: Brian Butcher, Randall J. Higuchi, Yun Wang
  • Patent number: 8984379
    Abstract: A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 17, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Bradley Engel, Brian Butcher
  • Publication number: 20120311396
    Abstract: A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Bradley Engel, Brian Butcher
  • Publication number: 20070159735
    Abstract: Methods (300, 400) and apparatus (46, 416, 470) are provided for sensing physical parameters. The apparatus (46, 416, 470) comprises a magnetic tunnel junction (MTJ) (32, 432), a magnetic field source (MFS) (34, 445, 476) whose magnetic field (35) overlaps the MTJ (32, 432) and a moveable magnetic cladding element (33, 448, 478) whose proximity (43, 462, 479, 479?) to the MFS (34, 445, 476) varies in response to an input to the sensor. The MFS (34, 445, 476) is located between the cladding element (33, 448, 478) and the MTJ (32, 432). Motion (41, 41?, 41-1, 464, 477) of the cladding element (33, 448, 478) relative to the MFS (34, 445, 476) in response to sensor input causes the magnetic field (35) at the MTJ (32, 432) to change, thereby changing the electrical properties of the MTJ (32, 432). A one-to-one correspondence (54) between the sensor input and the electrical properties of the MTJ (32, 432) is obtained.
    Type: Application
    Filed: October 19, 2006
    Publication date: July 12, 2007
    Inventors: Brian Butcher, Kenneth Smith, Bradley Engel
  • Publication number: 20060170068
    Abstract: Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Inventors: J. Ren, Brian Butcher, Mark Durlam, Gregory Grynkewich
  • Publication number: 20060102970
    Abstract: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Inventors: Brian Butcher, Gregory Grynkewich, Kelly Kyler, Kenneth Smith, Richard Williams
  • Publication number: 20050208681
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Application
    Filed: May 9, 2005
    Publication date: September 22, 2005
    Inventors: Thomas Meixner, Gregory Grynkewich, Jaynal Molla, J. Ren, Richard Williams, Brian Butcher, Mark Durlam
  • Publication number: 20050164413
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 28, 2005
    Inventors: Thomas Meixner, Gregory Grynkewich, Jaynal Molla, J. Ren, Richard Williams, Brian Butcher, Mark Durlam
  • Publication number: 20050158992
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Mark Durlam, Jeffrey Baker, Brian Butcher, Mark Deherrera, John D'Urso, Earl Fuchs, Gregory Grynkewich, Kelly Kyler, Jaynal Molla, J. Ren, Nicholas Rizzo
  • Publication number: 20050130374
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Application
    Filed: February 2, 2005
    Publication date: June 16, 2005
    Inventors: Gregory Grynkewich, Brian Butcher, Mark Durlam, Kelly Kyler, Charles Synder, Kenneth Smith, Clarence Tracy, Richard Williams
  • Publication number: 20050020053
    Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.
    Type: Application
    Filed: August 19, 2004
    Publication date: January 27, 2005
    Inventors: Brian Butcher, Kenneth Smith, Clarence Tracy
  • Publication number: 20050009212
    Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 13, 2005
    Inventors: Gregory Grynkewich, Brian Butcher, Mark Durlam, Clarence Tracy
  • Patent number: 6812040
    Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: November 2, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kelly Kyler, Saied N. Tehrani, John J. D'urso, Gregory W. Grynkewich, Mark A. Durlam, Brian Butcher
  • Publication number: 20030175997
    Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
    Type: Application
    Filed: March 12, 2002
    Publication date: September 18, 2003
    Inventors: Kelly Kyler, Saied N. Tehrani, John J. D'urso, Gregory W. Grynkewich, Mark A. Durlam, Brian Butcher
  • Patent number: D916322
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 13, 2021
    Assignee: ZAMPTECH SUB LLC
    Inventors: Conor Miller, Brian Butcher