Abstract: A computer processing system and method for computing large-degree isogenies having a computer processor resident on an electronic computing device operably configured to execute computer-readable instructions programmed to perform a large-degree isogeny operation by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations.

Abstract: A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result.

Abstract: A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result

Abstract: A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

Abstract: A computer processing system that includes an elliptic curve computational unit in a computer processing device operably configured to perform an elliptic curve arithmetic operation with a sequence of field operations, receive an elliptic curve numerical input that includes at least one elliptic curve coefficient of an elliptic curve that is operably utilized in the elliptic curve arithmetic operation, receive an elliptic curve coefficient randomization numerical input that is operably configured for use in the elliptic curve arithmetic operation, compute a new and substantially equivalent elliptic curve representation for the elliptic curve coefficient of the elliptic curve by performing a field operation with the elliptic curve numerical input and the elliptic curve coefficient randomization numerical input, and utilize the new and substantially equivalent elliptic curve representation in the sequence of field operations, and having an arithmetic output port operably configured to output a numerical resu

Abstract: A computer processing system and method for computing large-degree isogenies having a computer processor resident on an electronic computing device operably configured to execute computer-readable instructions programmed to perform a large-degree isogeny operation by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations.

Abstract: A computer processing isogeny-based cryptosystem method and architecture having at least one cryptosystem controller operably configured to initiate and supervise isogeny-based cryptosystem operations, at least one read-only memory operably configured to read instruction sequences and constants used to perform operations within an isogeny-based cryptosystem, at least one random-access memory operably configured to read and write intermediate data for the isogeny-based cryptosystem, and at least one of an isogeny computational unit operably configured to perform isogeny-based arithmetic. The isogeny computational unit also includes a program control unit operably configured to control the operations within the isogeny-based cryptosystem through a sequence of instructions and an instruction control unit operably configured to control an arithmetic logic unit and random-access memory interactions that include loading and storing data to the least one random-access memory.

Abstract: A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.

Abstract: A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

Abstract: A computer processing system for validating isogeny-based cryptography keys having an electronic computing device with an isogeny-based cryptosystem operably configured to validate public keying material including an elliptic curve by simultaneously computing an elliptic curve supersingularity check along with an elliptic curve public point check.

Abstract: A computer processing system for validating isogeny-based cryptography keys having an electronic computing device with an isogeny-based cryptosystem operably configured to validate public keying material including an elliptic curve by simultaneously computing an elliptic curve supersingularity check along with an elliptic curve public point check.

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

Abstract: A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.

Abstract: A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of Fp2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

Abstract: A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of Fp2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.