Patents by Inventor Brian C. Lacey

Brian C. Lacey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7170324
    Abstract: A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: January 30, 2007
    Assignee: Agere Systems Inc.
    Inventors: Carol Ann Huber, John C. Kriz, Brian C. Lacey, Bernard L. Morris
  • Patent number: 5514979
    Abstract: Disclosed is a bus driver circuit that dynamically clamps the bus voltage for a predetermined period following a transition of the bus voltage, thereby reducing overshoot and ringing. The disclosed circuit dynamically clamps the initial overshoot at approximately the bus terminating voltage VT. The clamping is dynamic in that it is active for only a limited, prescribed period, which is adjustable. In a preferred embodiment, a driver receives an input signal (VIN) and provides an OUTPUT signal to a bus terminated with a terminating voltage (VT). A clamp circuit receives a CLAMP GATE signal and sinks current from the OUTPUT signal, thus reducing ringing and overshoot of the output signal. A delay circuit disables the clamp after a prescribed delay following a transition of the OUTPUT signal.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: May 7, 1996
    Assignee: Unisys Corporation
    Inventors: David F. Collins, Brian C. Lacey
  • Patent number: 5485107
    Abstract: Disclosed is a backplane driver circuit 14' that temporarily clamps its output (PAD) to the termination supply voltage (V.sub.term) during a low to high transition. This termination is applied for a limited period of time determined by the delay through an inverter 14'-15 and a transfer gate 14'-11. This circuit is effective in reducing both the inductive effects of quickly turning the driver off and reflections due to the backplane stubs (L1-L8). Another feature of the driver circuit is that the driver can be plugged into or pulled out of a running system for maintenance without turning the system off. In order to accomplish this, the driver goes into a high impedance state when its supply voltage is turned off.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: January 16, 1996
    Assignee: Unisys Corporation
    Inventors: Brian C. Lacey, David F. Collins