Abstract: A reconfigurable baseband filter for use in a multimode communication system is disclosed. One or more filter elements can each be configured as a plurality of sub-elements. The value of each of the filter elements can be varied by switching between at least two of the plurality of sub-elements. Switching noise within a desired passband can be reduced by switching at a rate that is greater than the desired passband. The switching noise in the passband can be further reduced by pseudo-randomly switching between the sub-elements. The filter can use a delta-sigma modulator to generate a pseudo-random switching signal.

Abstract: A resistor tuning network is disclosed that comprises a first resistor connected in parallel with a second variable resistor and a third resistor coupled in series with the first resistor and the second variable resistor. The second variable resistor comprises an R-2R ladder network having an input and first and second output terminals, with a first line having a plurality of first arms connected in series with the input and first output terminal and nodes between each pair of arms, each arm having an identical resistor R. A series of shunt arms, each with a 2R resistor and a switch, are selectively connected between the respective nodes and the first or second output terminal. The resistance of the resistor tuning network is tuned by varying the switch positions in the shunt arms in the R-2R ladder network.

Abstract: A reconfigurable baseband filter for use in a multimode communication system is disclosed. One or more filter elements can each be configured as a plurality of sub-elements. The value of each of the filter elements can be varied by switching between at least two of the plurality of sub-elements. Switching noise within a desired passband can be reduced by switching at a rate that is greater than the desired passband. The switching noise in the passband can be further reduced by pseudo-randomly switching between the sub-elements. The filter can use a delta-sigma modulator to generate a pseudo-random switching signal.

Abstract: A resistor tuning network for an RC filter has a first, fixed resistor and a second, variable resistance connected in parallel with the fixed resistor. The variable resistance is an R-2R ladder circuit having an input and first and second output terminals, with a first line having a plurality of first arms connected in series with the input and first output terminal and nodes between each pair of arms, each arm having an identical resistor R. A series of shunt arms are selectively connected between the respective nodes and the first or second output terminal. Each shunt arm has a 2R resistor and a switch in series, and each switch has a first, closed position connecting the shunt arm to the first output terminal and a second, open position connecting the shunt arm to the second output terminal, such that the resistance of the ladder network is varied dependent on the switch positions and is at a maximum value when all switches are closed and a minimum value when all switches are open.

Abstract: A resistor tuning network for an RC filter has a first, fixed resistor and a second, variable resistance connected in parallel with the fixed resistor. The variable resistance is an R-2R ladder circuit having an input and first and second output terminals, with a first line having a plurality of first arms connected in series with the input and first output terminal and nodes between each pair of arms, each arm having an identical resistor R. A series of shunt arms are selectively connected between the respective nodes and the first or second output terminal. Each shunt arm has a 2R resistor and a switch in series, and each switch has a first, closed position connecting the shunt arm to the first output terminal and a second, open position connecting the shunt arm to the second output terminal, such that the resistance of the ladder network is varied dependent on the switch positions and is at a maximum value when all switches are closed and a minimum value when all switches are open.

Abstract: A Sallen-Key filter circuit having an operational amplifier of unity gain is tuned by replacing a resistor of the circuit with an adjustable resistor ladder network. The ladder network has an input and first and second output terminals and a plurality of arms connected in series between the input and first output terminal. Each arm has a resistor R and a node separating each pair of adjacent arms, a shunt arm connected to each node, each shunt arm having a resistor which has a value which is a multiple of R and a switch in series. Each switch controls connection of the respective shunt arm to the first or second output terminal, such that the resistance of the ladder network is varied dependent on the switch positions. The first output terminal is connected to the amplifier output and the second output terminal is connected to the amplifier positive input.

Abstract: A one-shot current circuit generates a current for a desired period during an input signal transition, the desired period during an input signal transition being proportional to the edge rate of the input signal. The circuit includes a MOS transistor device which selectively conducts current between an input terminal and a current generating circuit. The current generating circuit can be a bipolar transistor having its base coupled to the input terminal and a main current path between a circuit output and a supply voltage.

Abstract: Output overvoltage protection circuitry for circuits operating at low voltages (e.g., 3 v) interfacing to a higher voltage operating circuit (e.g., 5 v bus). To prevent problems with a pull-up PMOS device at the output when the bus is pulled-up to the higher voltage, a voltage node is provided in the circuit which follows the output voltage or the low supply voltage, whichever is higher, and a sub-circuit is provided to generate logic signals indicating when the bus is pulled too high. The PMOS device is then shut-down to prevent damage to the circuit.

Abstract: A BiCMOS power driver circuit for interfacing to a bus comprises circuitry for channelling current from a power source to the base of a bipolar device to pull the output all the way down to within a bipolar V.sub.SAT voltage drop of ground, and then uses feedback to turn-off the pull-down circuit to conserve power. A similar circuit functions to provide Incident Wave Switching and Glitch Suppression by monitoring the voltage level at the output and sinking current as necessary to maintain a low logic level.

Abstract: A BiCMOS digital delay chain includes two signal paths coupled between an input terminal and an output terminal. The first signal path has two CMOS inverters coupled in series, while the second path has one CMOS inverter coupled to an BiNMOS inverter, with the latter being coupled to a BiCMOS pull-down circuit. By providing two signal paths between the input and output terminals of the delayed chain, a zero-static-power low-voltage circuit is obtained in which power-supply sensitivity is higher in one switching direction than in the other. This feature permits operation over a wide range of power supply potentials while minimizing changes in integrated circuit performance.

Abstract: A CMOS inverter circuit is provided which includes a compensation circuit which modifies the inverter threshold depending on changes in supply voltage and/or temperature. The inverter includes a standard CMOS inverter, current boosting circuitry and a reference signal generator. The input of the inverter is coupled to the current boosting circuitry. A reference signal is also coupled to the current boosting circuitry in order to change the effective PMOS to NMOS ratio of the inverter to control the input threshold over a range of supply voltages and/or temperatures. The reference signal generator generates a reference signal which is dependent upon changes in supply voltage and which can be controlled over a range of temperatures.

Abstract: A BiCMOS line driver that incorporates a fully-powered, zero- static power pull-down driver with a standard BiCMOS pullup in a novel parallel input signal path construction having substantially equal propagation delays to create a complementary signal driver with very high speed and extremely low skew in propagation.