Patents by Inventor Brian C Miller
Brian C Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963691Abstract: A surgical instrument, has an end effector that includes an ultrasonic blade, and a clamp arm that moves relative to the ultrasonic blade from an opened position toward an intermediate position and a closed position. The clamp arm is offset from the ultrasonic blade to define a predetermined gap in the intermediate position between the opened position and the closed position. A clamp arm actuator connects to the clamp arm and moves from an opened configuration to a closed configuration to direct the clamp arm from the opened position toward the intermediate position and the closed position. A spacer connects with the clamp arm to inhibit movement of the clamp arm from the intermediate position toward the closed position for maintaining the predetermined gap between the clamp arm and the ultrasonic blade.Type: GrantFiled: December 21, 2020Date of Patent: April 23, 2024Assignee: Cilag GmbH InternationalInventors: Ryan M. Asher, Brian D. Black, John E. Brady, Joseph Dennis, Geni M. Giannotti, Bryce L. Heitman, Timothy S. Holland, Joseph E. Hollo, Andrew Kolpitcke, Amy M. Krumm, Jason R. Lesko, Matthew C. Miller, David A. Monroe, Ion V. Nicolaescu, Rafael J. Ruiz Ortiz, Matthew S. Schneider, Richard C. Smith, Shawn C. Snyder, Sarah A. Worthington, Monica L. Rivard, Fajian Zhang
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Publication number: 20150349764Abstract: A circuit includes a flip-flop and a delay circuit integrated with the flip-flop, the delay circuit including at least one delay element, the flip-flop and delay circuit having a predefined architecture such that a delay provided by the delay circuit may have a selectable value while the flip-flop remains within the predefined architecture.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chun-Kiat Chua, Brian C. Miller
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Patent number: 8543967Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.Type: GrantFiled: February 24, 2012Date of Patent: September 24, 2013Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Jason T. Gentry, Brian C. Miller, William S. Burton, M. Jason Welch, Richard A. Krzyzkowski
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Publication number: 20130227508Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.Inventors: Jason T. Gentry, Brian C. Miller, William S. Burton, M. Jason Welch, Richard A. Krzyzkowski
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Patent number: 6744285Abstract: A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.Type: GrantFiled: August 8, 2002Date of Patent: June 1, 2004Assignee: Agilent Technologies, Inc.Inventors: Wayne G. Mangum, Brian C. Miller, Peter J. Meier, Cory Groth
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Patent number: 6703869Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.Type: GrantFiled: June 5, 2002Date of Patent: March 9, 2004Assignee: Agilent Technologies, Inc.Inventors: Darrin C. Miller, Brian C Miller, Robert H Miller, Jr.
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Publication number: 20040027166Abstract: A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.Type: ApplicationFiled: August 8, 2002Publication date: February 12, 2004Inventors: Wayne G. Mangum, Brian C. Miller, Peter J. Meier, Cory Groth
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Patent number: 6673125Abstract: A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.Type: GrantFiled: February 8, 2002Date of Patent: January 6, 2004Assignee: Milliken & CompanyInventors: Brian C. Miller, Raymond C. Sturm
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Publication number: 20030227298Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.Type: ApplicationFiled: June 5, 2002Publication date: December 11, 2003Inventors: Darrin C. Miller, Brian C. Miller, Robert H. Miller
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Publication number: 20030154553Abstract: A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.Type: ApplicationFiled: February 8, 2002Publication date: August 21, 2003Inventors: Brian C. Miller, Raymond C. Sturm
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Publication number: 20030157854Abstract: A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.Type: ApplicationFiled: February 8, 2002Publication date: August 21, 2003Inventors: Brian C. Miller, Raymond C. Sturm
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Patent number: 6602437Abstract: A chemically modified nonwoven textile article and method for producing the same is provided that exhibits pilling resistance, soil release, strength, and abrasion resistance properties, thus rendering the article less prone to the formation of objectionable pill balls, staining, or loss of strength, thereby increasing wearer comfort and retaining the desired appearance of the article, and thereby extending the useful life of the article. A composition of matter for chemically modifying a nonwoven textile article to achieve pilling resistance, soil release, strength, and abrasion resistance is also provided.Type: GrantFiled: February 8, 2002Date of Patent: August 5, 2003Assignee: Millikien & CompanyInventors: Brian C. Miller, Raymond C. Sturm
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Patent number: 6567966Abstract: Systems and methods are presented for decreasing the effect of Miller capacitance on adjacent interconnects in an integrated circuit. The systems and methods include interweaving interconnects with signals traveling in one direction with interconnects with signals traveling in the opposite direction. The systems include a system for fabricating integrated circuits with interweaved interconnects and an integrated circuit with interweaved interconnects.Type: GrantFiled: February 14, 2001Date of Patent: May 20, 2003Assignee: Agilent Technologies, Inc.Inventor: Brian C. Miller
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Patent number: 6539507Abstract: An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.Type: GrantFiled: November 10, 1999Date of Patent: March 25, 2003Assignee: Agilent Technologies, Inc.Inventors: Christopher M Juenemann, Bradley J Goertzen, Rory L Fisher, Randy L Fiscus, Brian C Miller, Peter J Meier, Joel Buck-Gengler, Kenneth S Bower, Michael R Diehl, Dale R Beucler
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Publication number: 20020112220Abstract: Systems and methods are presented for decreasing the effect of Miller capacitance on adjacent interconnects in an integrated circuit. The systems and methods include interweaving interconnects with signals traveling in one direction with interconnects with signals traveling in the opposite direction. The systems include a system for fabricating integrated circuits with interweaved interconnects and an integrated circuit with interweaved interconnects.Type: ApplicationFiled: February 14, 2001Publication date: August 15, 2002Inventor: Brian C. Miller
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Patent number: 6429683Abstract: An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.Type: GrantFiled: August 16, 2000Date of Patent: August 6, 2002Assignee: Agilent Technologies, Inc.Inventors: Darrin C. Miller, Brian C Miller
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Patent number: 6124869Abstract: A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.Type: GrantFiled: May 20, 1998Date of Patent: September 26, 2000Assignee: Agilent TechnologiesInventors: Brian C. Miller, Peter J. Meier
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Patent number: 6073261Abstract: The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit.Type: GrantFiled: May 22, 1998Date of Patent: June 6, 2000Assignee: Hewlett Packard CompanyInventor: Brian C. Miller
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Patent number: 5847969Abstract: An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.Type: GrantFiled: May 1, 1996Date of Patent: December 8, 1998Assignee: Hewlett-Packard Co.Inventors: Brian C. Miller, Peter J. Meier
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Patent number: 5831991Abstract: Apparatus for electrically verifying a functional unit contained within an integrated circuit comprises a functional unit, a state machine, a number of integrated circuit input pins, and means for alternately providing the functional unit with control data derived from the state machine, and control data derived from the number of integrated circuit input pins. The means for providing control data from alternating sources comprises a multiplexor which receives a first set of inputs from the state machine, and a second set of inputs from a test control block. The test control block monitors various of the integrated circuit input pins for a designated instruction, receives control data via the input pins, and controls the operation of the multiplexor. The test control block comprises a number of test registers which can be configured to receive two or more states of control data.Type: GrantFiled: December 13, 1996Date of Patent: November 3, 1998Assignee: Hewlett-Packard Co.Inventors: Brian C. Miller, Alan S. Krech, Jr.