Patents by Inventor Brian C. Twichell

Brian C. Twichell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180059957
    Abstract: A computer-implemented method comprises identifying a storage subsystem comprising one or more storage address units and associated with one or more access interfaces; identifying an address-interface correlation conclusion; and identifying a target address unit identification associated with at least of the one or more storage address units. The computer-implemented method further comprises determining a target interface conclusion associated with at least one of the one or more access interfaces based on the address-interface correlation guideline and the target address unit identification. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Sergio Reyes, Brian C. Twichell
  • Patent number: 9886332
    Abstract: Storage system and application intercommunication is provided. A first kernel-mode module determines a first event corresponding to an operational parameter of a first node based, at least in part, on a shared namespace accessible by the first kernel-mode module and a second kernel-mode module. An interrupt is issued based on the first event from the first kernel-mode module to the second kernel-mode module via an interface. The second kernel-mode module issues a second event to a second node, wherein the second event corresponds to the object of the shared namespace.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Faisal Ahmed, Brian C. Twichell
  • Patent number: 9864531
    Abstract: Determining a preferred interface for write access to a data storage system having multiple interfaces. Interface preference is determined at the data-stripe level. Write requests are routed to the preferred interface.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Faisal Ahmed, Brian C. Twichell
  • Publication number: 20160335003
    Abstract: Determining a preferred interface for write access to a data storage system having multiple interfaces. Interface preference is determined at the data-stripe level. Write requests are routed to the preferred interface.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 17, 2016
    Inventors: Faisal Ahmed, Brian C. Twichell
  • Publication number: 20160328277
    Abstract: Storage system and application intercommunication is provided. A first kernel-mode module determines a first event corresponding to an operational parameter of a first node based, at least in part, on a shared namespace accessible by the first kernel-mode module and a second kernel-mode module. An interrupt is issued based on the first event from the first kernel-mode module to the second kernel-mode module via an interface. The second kernel-mode module issues a second event to a second node, wherein the second event corresponds to the object of the shared namespace.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 10, 2016
    Inventors: Faisal Ahmed, Brian C. Twichell
  • Patent number: 9021206
    Abstract: A method, system and program are provided for controlling access to a specified cache level in a cache hierarchy in a multiprocessor system by evaluating cache statistics for a specified application at the specified cache level against predefined criteria to prevent the specified application from accessing the specified cache level if the specified application does not meeting the predefined criteria.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, Brian C. Twichell, Greg R. Mewhinney, David B. Whitworth
  • Patent number: 8954645
    Abstract: Performing storage writes in a mirrored virtual machine system by receiving a state of a primary virtual machine during execution of an application, wherein the primary virtual machine runs on a first physical machine and a secondary virtual machine runs on a second physical machine, wherein the state is captured by checkpointing, and the primary virtual machine is configured to write data to a first block and concurrently write the data to a write buffer on the secondary virtual machine. The method also includes storing a copy of data within a second block to a rollback buffer for the secondary virtual machine, in response to identifying a checkpoint in the application, merging the rollback buffer with the write buffer, in response to detecting a failover, writing a copy of the rollback buffer to the disk storage, and continuing execution on the secondary virtual machine from the last checkpoint.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Geraint North, Adam McNeeney, Bruce G. Mealey, Brian C. Twichell
  • Patent number: 8539453
    Abstract: In an embodiment, a kernel performs autonomic input/output tracing and performance tuning. A first table is provided in a device driver framework and a second table in a kernel of a computer. An input/output device monitoring tool is provided in the device driver framework. A plurality of instructions in the kernel compares each value in the first table with each value in the second table. Responsive to a match of a value in the first table and a value in the second table, the kernel automatically runs a command line to perform a system trace, a component trace, or a tuning task. The first table is populated with a plurality of values calculated from a plurality of data in a plurality of device memories and in the controller memory and the second table is populated in accordance with a second plurality of inputs to the command line interface.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, Greg R. Mewhinney, Brian C. Twichell, David B. Whitworth
  • Publication number: 20130054897
    Abstract: A method, system and program are provided for controlling access to a specified cache level in a cache hierarchy in a multiprocessor system by evaluating cache statistics for a specified application at the specified cache level against predefined criteria to prevent the specified application from accessing the specified cache level if the specified application does not meeting the predefined criteria.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane G. Flemming, Brian C. Twichell, Greg R. Mewhinney, David B. Whitworth
  • Publication number: 20120191908
    Abstract: Performing storage writes in a mirrored virtual machine system by receiving a state of a primary virtual machine during execution of an application, wherein the primary virtual machine runs on a first physical machine and a secondary virtual machine runs on a second physical machine, wherein the state is captured by checkpointing, and the primary virtual machine is configured to write data to a first block and concurrently write the data to a write buffer on the secondary virtual machine. The method also includes storing a copy of data within a second block to a rollback buffer for the secondary virtual machine, in response to identifying a checkpoint in the application, merging the rollback buffer with the write buffer, in response to detecting a failover, writing a copy of the rollback buffer to the disk storage, and continuing execution on the secondary virtual machine from the last checkpoint.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 26, 2012
    Applicant: International Business Machines Corporation
    Inventors: Geraint North, Adam McNeeney, Bruce G. Mealey, Brian C. Twichell
  • Publication number: 20120005580
    Abstract: In an embodiment, a kernel performs autonomic input/output tracing and performance tuning. A first table is provided in a device driver framework and a second table in a kernel of a computer. An input/output device monitoring tool is provided in the device driver framework. A plurality of instructions in the kernel compares each value in the first table with each value in the second table. Responsive to a match of a value in the first table and a value in the second table, the kernel automatically runs a command line to perform a system trace, a component trace, or a tuning task. The first table is populated with a plurality of values calculated from a plurality of data in a plurality of device memories and in the controller memory and the second table is populated in accordance with a second plurality of inputs to the command line interface.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane G. Flemming, Greg R. Mewhinney, Brian C. Twichell, David B. Whitworth
  • Patent number: 5446876
    Abstract: An improved instruction tracing mechanism provides a combination of hardware, internal to the CPU, and novel software. Additional registers are added to interconnected to the CPU. These registers store values indicating the instruction address, data address, whether the instruction was a load or store, the number of bytes moved and whether any address mapping changes occurred. The registers are read by a trace interrupt handler which then provides the information to a trace buffer and a profile buffer. The end user can then access the trace and profile information through the input/output (I/O) system of the data processing system.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Frank E. Levine, Brian C. Twichell, Edward H. Welbon