Patents by Inventor Brian Chase Twichell

Brian Chase Twichell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11593004
    Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian Chase Twichell
  • Publication number: 20230051684
    Abstract: Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Sergio Reyes, Brian Chase Twichell
  • Publication number: 20220318337
    Abstract: An approach for classifying ordered data. The approach can calculate a cumulative sum (CUSUM) chart for an ordered dataset and determine a peak and valley for the CUSUM chart. The approach can plot three rays, a first ray between the beginning of the CUSUM chart and the peak/valley, a second ray between select the peak/valley and the peak/valley and a third ray between the peak/valley and the end of the CUSUM chart. The approach can calculate three angles formed by the three rays and an x-axis associated with the CUSUM chart. It should be noted that the sign of the angle matches the sign of the slope of the ray. The approach can translate the three angles to three symbols based on a translation table associated with an ordered character set and generate a classification based on concatenating the three symbols.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Sergio Reyes, Samuel Kipling Ingram, Brian Chase Twichell, Yijie Zhang
  • Patent number: 6442664
    Abstract: A memory translation system which includes an “address cache” (addrcache). This address cache contains translation information of recently referenced addresses, and is accessed before the conventional two-level address translation process. If a hit is made in the address cache, which does not require protection checking, the conventional address translation process is bypassed. The address cache stores its memory addresses according to the protection status of each address, so that protection checking is not performed as a separate step.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ann Marie Maynard, Brian Chase Twichell