Patents by Inventor Brian Cherek

Brian Cherek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12052016
    Abstract: An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 30, 2024
    Assignee: Microchip Technology Corporation
    Inventors: Sridhar Devulapalli, Daniel J. Russell, Brian Cherek, Michael Klein
  • Publication number: 20210409024
    Abstract: An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 30, 2021
    Inventors: Sridhar Devulapalli, Daniel J. Russell, Brian Cherek, Michael Klein
  • Publication number: 20060132223
    Abstract: A voltage reference circuit is disclosed. The circuit comprises a PTAT bias generator circuit and a band gap transistor voltage system coupled to the operational amplifier system. The band gap voltage system includes at least one diode-connected CMOS transistor. The advantage of this configuration is that the diode-connected CMOS device allows for a lower output voltage level than a bipolar device, particularly at colder temperatures. This allows for lower overall operating voltage for the device. The present invention provides for the creation of a temperature-stable reference voltage at a supply voltage and/or operating temperature lower than conventional circuits.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventor: Brian Cherek