Abstract: A speech detection circuit (SDC). The SDC includes a first-in, first-out (FIFO) memory array, a multiplier, a summer, a fast Fourier transformer, a counter, an RMS comparator, and a sparsity comparator. The FIFO stores a plurality of data samples. The multiplier squares the data samples. The summer sums the plurality of squared data samples. The fast Fourier transformer performs an FFT on the plurality of data samples. The counter counts a quantity of the plurality of data samples that exceed a spectral threshold. The RMS comparator compares the summed plurality of squared data samples to an RMS threshold, the quantity of which are compared to a sparsity threshold. The SDC then outputs a wakeup signal when the summed plurality of squared data samples exceeds the RMS threshold and the quantity of the plurality of data samples that exceed the spectral threshold is less than the sparsity threshold.