Patents by Inventor Brian Clerkin

Brian Clerkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8666722
    Abstract: In a STA method, after accessing data sets regarding the IC, vectors of the data sets for STA can be generated. Each vector can include a base value and a plurality of tokens, wherein each token is quantized. For each vector, the data of the vector can be adjusted. Adjusting can include shifting a predetermined token to zero and adjusting the base value and remaining token values based on the shifting. Incremental compression can be applied within the vector by storing each token value as a difference versus its previous token value. Differential compression can then be applied by storing each token value as a difference versus a corresponding token value in a predetermined reference vector. A resulting vector can be stored. At this point, an operation for STA can be performed using multiple resulting vectors without de-quantizing or decompressing.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: March 4, 2014
    Assignee: Synopsys, Inc.
    Inventors: Jinfeng Liu, Brian Clerkin, Feroze P. Taraporevala
  • Patent number: 8261220
    Abstract: Partitioning of a design allows static timing analysis (STA), signal integrity, and noise analysis to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime and throughput of the analysis can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA and ensure minimal inter-partition data dependency during the analysis. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of the analysis can be optimized without compromising the accuracy and quality of results.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 4, 2012
    Assignee: Synopsys, Inc.
    Inventors: Qiuyang Wu, Brian Clerkin
  • Publication number: 20110307226
    Abstract: In a STA method, after accessing data sets regarding the IC, vectors of the data sets for STA can be generated. Each vector can include a base value and a plurality of tokens, wherein each token is quantized. For each vector, the data of the vector can be adjusted. Adjusting can include shifting a predetermined token to zero and adjusting the base value and remaining token values based on the shifting. Incremental compression can be applied within the vector by storing each token value as a difference versus its previous token value. Differential compression can then be applied by storing each token value as a difference versus a corresponding token value in a predetermined reference vector. A resulting vector can be stored. At this point, an operation for STA can be performed using multiple resulting vectors without de-quantizing or decompressing.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Applicant: Synopsys, Inc.
    Inventors: Jinfeng Liu, Brian Clerkin, Feroze P. Taraporevala
  • Publication number: 20110131540
    Abstract: Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of STA can be optimized without compromising the accuracy and quality of results.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: Synopsys, Inc.
    Inventors: Qiuyang Wu, Brian Clerkin
  • Patent number: 7739098
    Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: June 15, 2010
    Assignee: Synopsys, Inc.
    Inventors: Kayhan Küçükçakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew J. Seigel
  • Publication number: 20050172250
    Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.
    Type: Application
    Filed: February 4, 2004
    Publication date: August 4, 2005
    Applicant: Synopsys, Inc.
    Inventors: Kayhan Kucukcakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew Seigel