Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: A conference server enables collaborative communications among a variety of client processes of varying configurations all operatively coupled over a computer network to each other and to the server. The server receives audio streams from participating client processes in a conference, selects which audio streams are active, and broadcasts one or more of the active audio streams to the client processes participating in the conference depending on the clients receiving capabilities and the conference parameters. The client processes receiving multiple active audio streams perform mixing locally at the client node. Without having to perform mixing at the server, resources are saved and the number of simultaneous participating client processes to the conference may be increased accordingly. The server is further capable of simultaneously accommodating multipoint clients and non-multipoint H.323 clients, as well as operating in multiway and “push to talk” modes.

Abstract: A system for session failover management in a server cluster environment, the system including one or more clusters, each cluster having one or more servers, each server having one or more partition, each partition identified by a partition ID and grouping one or more sessions, and a failover manager configured to detect the failure of any of the servers and effect the assignment any of the partitions on the failed server to another of the servers within the failed server's cluster.

Abstract: A dynamic load fixture (DLF) applies a torsion load to a unit under test (UUT) to achieve the demanding aerodynamic load exposures encountered by a control actuation system (CAS) in flight. Instead of fixing the end of the torsion bar, the DLF controls the application of torque to the torsion bar, hence the UUT via a DLF motor. The dynamic load can be independent of the angular rotation of the UUT, which allows the DLF to more effectively reproduce desired acceptance tests such as torque-at-rate and nonlinear loads. Furthermore, application of the loads through a torsion bar allows the system the compliance needed to generate precise loads while allowing for the flexibility of changing torsion bars to test a wide variety of UUT on one test platform. To achieve the demanding aerodynamic load exposures encountered by a CAS in flight, the controller must be able to respond both very fast and very precisely.

Abstract: A system and method is provided that includes a communication system for handling Session Initiation Protocol (SIP) messages. The system includes a plurality of first servers for processing a first and a second message. The system also includes a plurality of second servers, which may include a mapping/correlating function for receiving the first message from a client and sending the first message to the plurality of first servers based on associating the first message with a resource. The second message received from the plurality of first servers is sent to the client based on stored routing information associated with the client, whereby the stored routing information resides within the plurality of second servers.