Patents by Inventor Brian Condie
Brian Condie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908823Abstract: A packaged semiconductor device includes a first bond pad, a second bond pad, a first bond wire that includes a first end bonded to the first bond pad and a second end bonded to the second bond pad, and a second bond wire that includes a first end that is electrically connected to the first bond pad and a second end that is electrically connected to the second bond pad. The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.Type: GrantFiled: January 11, 2021Date of Patent: February 20, 2024Assignee: Wolfspeed, Inc.Inventors: Erwin Orejola, Brian Condie, Ulf Andre
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Publication number: 20220223559Abstract: A packaged semiconductor device includes a first bond pad, a second bond pad, a first bond wire that includes a first end bonded to the first bond pad and a second end bonded to the second bond pad, and a second bond wire that includes a first end that is electrically connected to the first bond pad and a second end that is electrically connected to the second bond pad. The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.Type: ApplicationFiled: January 11, 2021Publication date: July 14, 2022Inventors: Erwin Orejola, Brian Condie, Ulf Andre
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Patent number: 9293407Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal and a second terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.Type: GrantFiled: November 3, 2014Date of Patent: March 22, 2016Assignee: Infineon Technologies AGInventors: Alexander Komposch, Soon Ing Chew, Brian Condie
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Publication number: 20150048492Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.Type: ApplicationFiled: November 3, 2014Publication date: February 19, 2015Inventors: Alexander Komposch, Soon Ing Chew, Brian Condie
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Patent number: 8907467Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.Type: GrantFiled: March 28, 2012Date of Patent: December 9, 2014Assignee: Infineon Technologies AGInventors: Alexander Komposch, Soon Ing Chew, Brian Condie
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Publication number: 20130256858Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.Type: ApplicationFiled: March 28, 2012Publication date: October 3, 2013Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Alexander Komposch, Soon Ing Chew, Brian Condie
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Publication number: 20070235855Abstract: A wirebond array (100) comprising a plurality of signal wires 110 and a plurality of ground wires (120) interdigitated with and substantially parallel to the set of signal wires (110). In one embodiment, each of the plurality of signal wires (110) and ground wires (120) is attached to a first semiconductor device (102) (e.g., a microwave power device). In another, each of the plurality of signal wires (110) is further attached to a package lead (104). In one embodiment, each of the plurality of ground wires (120) is further attached to a ground connection region (106) substantially coplanar with the package lead (104). Alternatively, each of the plurality of signal wires (110) is further attached to a second semiconductor device, wherein each of the plurality of ground wires (120) is further attached to the second semiconductor device.Type: ApplicationFiled: March 29, 2006Publication date: October 11, 2007Inventors: Mario Bokatius, Peter Aaen, Brian Condie
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Publication number: 20070090545Abstract: Structure and method are provided for plastic encapsulated semiconductor devices. The encapsulation comprises a plastic binder having a dielectric constant ?b and loss tangent ?b and a filler mixed therewith having lower ?f and/or ?f so that ?m and/or ?m of the mix is less than ?b, ?b, respectively. Hollow microspheres of varied sizes are preferred fillers, desirably in the size range of about 0.3 to 300 micrometers. These should comprise at least about 50%, more preferably 60 to 70% or more of the mixture by volume so that the resulting mix has ?m<3, preferably <2.5 and ?m<0.005. The encapsulant mixture is placed in proximity to or on the die so that the fringing electric fields of the die, die wiring and/or die connections are exposed to a lower ? and/or ? than that of a plastic encapsulation without the filler.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Mahesh Shah
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Publication number: 20070090543Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die are coated with the buffer layer. The buffer layer is patterned to expose the die bonding pads but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Mahesh Shah
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Publication number: 20070090542Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Mali Mahalingam, Mahesh Shah
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Publication number: 20070090514Abstract: A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Lakshminarayan Viswanathan, Richard Wetz
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Publication number: 20070090515Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Brian Condie, Lakshminarayan Viswanathan, Richard Wetz
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Publication number: 20060292827Abstract: A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a first die section (210), a second die section (212) adjacent the first die section (210), and a strip (216) connecting the first die section (210) and the second die section (212), removing material from portions of the non-active surface of the substrate (206) on which the backing material (104) is not deposited to thereby partially separate the substrate (200) into a first die (236) and a second die (238) connected to one another by the strip (254) of the deposited backing material, and breaking the strip connector (254) to separate the first die (236) from the second die (238).Type: ApplicationFiled: June 22, 2005Publication date: December 28, 2006Inventors: Brian Condie, David Dougherty, Mahesh Shah
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Publication number: 20060211111Abstract: The present invention provides compositions and methods for mammalian neural cell production, their stabilization and their proliferation. More particularly, the present invention provides cellular differentiation methods employing culturing the cells on a cell line or in cell culture and further contacting the cells with MEDII conditioned medium for the generation of stable mammalian neural cells from pluripotent mammalian stem cells. The invention further provides methods for the stabilization of a neural cell in culture comprising contacting the neural cell with MEDII conditioned medium. Preferably, the stabilized neural cell is a neural progenitor cell.Type: ApplicationFiled: December 18, 2003Publication date: September 21, 2006Inventors: Maisam Mitalipova, Ian Lyons, Brian Condie, Allan Robins, Scott Noggle
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Publication number: 20060194315Abstract: The current invention relates to the control and/or manipulation of the gamma-secretase signaling pathway in pluripotent cells to stabilize the cells in a pluripotent state and/or to control the differentiation of the pluripotent cells towards a differentiated state. The invention further includes feeder layers that contain or express ligands or other compounds that inhibit gamma-secretase or Notch signaling to enhance the maintenance of pluripotent cells in a pluripotent state. The invention also includes cell culture compositions that comprise pluripotent cells and inhibitors of gamma-secretase, or activators or inhibitors of Notch signaling.Type: ApplicationFiled: March 31, 2004Publication date: August 31, 2006Inventors: Brian Condie, Allan Robins, Scott Noggle
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Publication number: 20060121607Abstract: The present invention provides compositions and methods for human neural cell production. More particularly, the present invention provides cellular differentiation methods employing an essentially serum free MEDII conditioned medium for the generation of human neural cells from pluripotent and multipotent human stem cells.Type: ApplicationFiled: August 8, 2003Publication date: June 8, 2006Inventors: Thomas Schulz, Steven Stice, Brian Condie, Bruce Davidson
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Publication number: 20060014280Abstract: The present invention provides compositions and methods for human neural cell production. More particularly, the present invention provides cellular differentiation methods employing amphiphilic lipid compounds, preferably ceramide analogs of the ?-hydroxyalkylamine type and optionally employing an essentially serum free MEDII conditioned medium for the generation of human neural cells from pluripotent human cells. The methods alternatively comprise modulating apoptosis by modifying the levels of PAR-4, with or without the presence of amphiphilic lipid compounds and optionally employing MEDII conditioned medium. The methods alternatively encompass modulating apoptosis by modulating the intracellular concentration of endogenous lipid second messengers, such as ceramide.Type: ApplicationFiled: September 25, 2003Publication date: January 19, 2006Inventors: Brian Condie, Erhard Bieberich