Abstract: A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.

Abstract: A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.

Abstract: Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection.

Abstract: Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.

Abstract: Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection.

Abstract: Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.