Patents by Inventor Brian Creed
Brian Creed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940254Abstract: A projectile designed to be lead-free and have a ballistic coefficient ranging from about 0.13 to about 0.80 or greater for enhanced energy/performance at extended ranges may have an elongated body formed with a jacket including a wall having an end defining an ogive portion and a cavity or recess defined within the jacket and in which a core is received. The projectile can be configured in various calibers and sizes. The projectile core may be formed from a plurality of core sections, and at least one of the plurality of core sections may include tungsten powder and a lead-free binder material pressed together to form a substantially cylindrical shape or compact. One or more of the core sections further can be sintered, and the one or more core sections may be received in an end-to-end relationship within the cavity defined by the jacket to form a stacked, sectional core.Type: GrantFiled: July 11, 2022Date of Patent: March 26, 2024Assignee: Barnes Bullets, LLCInventors: Jason Wesley Robbins, Carl Carter, Christopher Creed Crosby, Gregory S. Christensen, Mitchell Dean Kukson, Brian James Simons, Greggory Sloan, Michael Painter
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Patent number: 11569393Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: March 9, 2020Date of Patent: January 31, 2023Assignee: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence E. Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 11552663Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.Type: GrantFiled: December 9, 2020Date of Patent: January 10, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
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Publication number: 20210091815Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.Type: ApplicationFiled: December 9, 2020Publication date: March 25, 2021Applicant: Huawei Technologies Co., Ltd.Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
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Publication number: 20200321479Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: March 9, 2020Publication date: October 8, 2020Applicant: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence E. Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 10715195Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.Type: GrantFiled: June 13, 2018Date of Patent: July 14, 2020Assignee: Futurewei Technologies, Inc.Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
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Patent number: 10586878Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: December 4, 2017Date of Patent: March 10, 2020Assignee: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Publication number: 20190386694Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.Type: ApplicationFiled: June 13, 2018Publication date: December 19, 2019Applicant: Futurewei Technologies, Inc.Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
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Publication number: 20180090627Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: December 4, 2017Publication date: March 29, 2018Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 9837555Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: April 15, 2015Date of Patent: December 5, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Publication number: 20160308073Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: April 15, 2015Publication date: October 20, 2016Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 6664826Abstract: A loop filter and amplifier (206) is configured to generate a control voltage (VC) by applying low gain to a correction voltage (VP) in response to an input signal (VH/L) indicating that the VCO (202) is to operate at low frequencies and applying high gain to the correction voltage in response to the input signal indicating that the VCO is to operate at high frequencies. A loop filter and amplifier (306) is configured to generate a control voltage (VC) by shifting the control voltage by an amount determined by an offset voltage (VOFF) and by adjusting the control voltage with a correction voltage (VP). An operational amplifier (310) is configured to generate a difference between the amount determined by the offset voltage and the correction voltage.Type: GrantFiled: July 20, 2000Date of Patent: December 16, 2003Assignee: Motorola, Inc.Inventors: Brian Creed, David J. Smentek, William C. Hart