Patents by Inventor Brian Curran
Brian Curran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11663315Abstract: A computer system for just-in-time authentication displays a user interface comprising a first portion and a second portion. The first portion of the user interface is associated with a first permission attribute, and the second portion of the user interface is associated with a second permission attribute. The first permission attribute is associated with a first user and the second permission attribute is associated with a second user. The computer system receives, from one or more proximity sensors, a proximity of the second user relative to the user interface. The computer system also receives, from an identity-verification sensor, a verification of an identification of the second user. Further, the computer system activates the second portion of the user interface for interaction from the second user.Type: GrantFiled: January 29, 2021Date of Patent: May 30, 2023Assignee: MasterControl Solutions, Inc.Inventors: Chad Milito, Terrance Lanham Holbrook, Brian Curran, Alan Rencher
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Patent number: 11223703Abstract: Various embodiments are provided for implementing instruction initialization in a dataflow architecture in a computing environment. A data packet may be transmitted from a selected node to one or more of a plurality of nodes using one or more existing data paths in an initialization network. A determination operation is performed to determine whether one or more of a plurality of nodes is a target node intended for the data packet. Those of the plurality of nodes determined to be a target node initialize one or more components of the target node using the data packet. The data packet may be forwarded by each of the one or more of a plurality of nodes to a subsequent node in the initialization network.Type: GrantFiled: March 19, 2019Date of Patent: January 11, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Curran, Bruce Fleischer, Kailash Gopalakrishnan, Sunil K Shukla
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Publication number: 20210342435Abstract: A computer system for just-in-time authentication displays a user interface comprising a first portion and a second portion. The first portion of the user interface is associated with a first permission attribute, and the second portion of the user interface is associated with a second permission attribute. The first permission attribute is associated with a first user and the second permission attribute is associated with a second user. The computer system receives, from one or more proximity sensors, a proximity of the second user relative to the user interface. The computer system also receives, from an identity-verification sensor, a verification of an identification of the second user. Further, the computer system activates the second portion of the user interface for interaction from the second user.Type: ApplicationFiled: January 29, 2021Publication date: November 4, 2021Inventors: Chad Milito, Terrance Lanham Holbrook, Brian Curran, Alan Rencher
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Patent number: 10838868Abstract: Embodiments for implementing a communicating memory between a plurality of computing components are provided. In one embodiment, an apparatus comprises a plurality of memory components residing on a processing chip, the plurality of memory components interconnected between a plurality of processing elements of at least one processing core of the processing chip and at least one external memory component external to the processing chip. The apparatus further comprises a plurality of load agents and a plurality of store agents on the processing chip, each interfacing with the plurality of memory components. Each of the plurality of load agents and the plurality of store agents execute an independent program specifying a destination of data transacted between the plurality of memory components, the at least one external memory component, and the plurality of processing elements.Type: GrantFiled: March 7, 2019Date of Patent: November 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chia-Yu Chen, Jungwook Choi, Brian Curran, Bruce Fleischer, Kailash Gopalakrishan, Jinwook Oh, Sunil K Shukla, Vijayalakshmi Srinivasan, Swagath Venkataramani
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Publication number: 20200304598Abstract: Various embodiments are provided for implementing instruction initialization in a dataflow architecture in a computing environment. A data packet may be transmitted from a selected node to one or more of a plurality of nodes using one or more existing data paths in an initialization network. A determination operation is performed to determine whether one or more of a plurality of nodes is a target node intended for the data packet. Those of the plurality of nodes determined to be a target node initialize one or more components of the target node using the data packet. The data packet may be forwarded by each of the one or more of a plurality of nodes to a subsequent node in the initialization network.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian CURRAN, Bruce FLEISCHER, Kailash GOPALAKRISHNAN, Sunil K SHUKLA
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Publication number: 20200285579Abstract: Embodiments for implementing a communicating memory between a plurality of computing components are provided. In one embodiment, an apparatus comprises a plurality of memory components residing on a processing chip, the plurality of memory components interconnected between a plurality of processing elements of at least one processing core of the processing chip and at least one external memory component external to the processing chip. The apparatus further comprises a plurality of load agents and a plurality of store agents on the processing chip, each interfacing with the plurality of memory components. Each of the plurality of load agents and the plurality of store agents execute an independent program specifying a destination of data transacted between the plurality of memory components, the at least one external memory component, and the plurality of processing elements.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chia-Yu CHEN, Jungwook CHOI, Brian CURRAN, Bruce FLEISCHER, Kailash GOPALAKRISHAN, Jinwook OH, Sunil K. SHUKLA, Vijayalakshmi SRINIVASAN, Swagath VENKATARAMANI
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Patent number: 10205623Abstract: A method and system for the efficient customization of website tracking data includes a data collector with a user interface for assigning custom events and attributes to events occurring on a website. The data collector receives custom tracking data from the website in response to the occurrence of an event to be tracked. Customization of tracking data is achieved through the use of an embedded tracking code and associated data collection file. The embedded tracking code is configured to report tracking data customized for the website. The data collection server is configured via a graphical user interface to receive and store the customized tracking data. A configuration string from the data collector is inserted into the data collection file on the web site. In this manner, the data collection server and website is customized to collect customized tracking data efficiently without assistance from others.Type: GrantFiled: June 26, 2003Date of Patent: February 12, 2019Assignee: Adobe Systems IncorporatedInventors: Brett Error, Chris Error, Brian Curran
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Patent number: 10151783Abstract: An apparatus and a method for determining an antenna characteristic of an antenna under test in free space is disclosed. Measurement results of a transmitted power of a measurement signal transmitted between the reference antenna and an antenna under test are detected, wherein detecting takes place in the frequency domain. The detected measurement results are transformed into the time domain and a time-domain filter is applied to the measurement results converted into the time domain. A filter width of the time-domain filter is determined in dependence on a spatial distance between the reference antenna and the antenna under test. Measurement result portions that result due to a multipath propagation of the measurement signal between the reference antenna and the antenna under test are reduced or removed.Type: GrantFiled: September 29, 2017Date of Patent: December 11, 2018Assignees: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V., Technische Universitaet BerlinInventors: Ivan Ndip, Volker Grosser, Christian Tschoban, Brian Curran, Max Huhn, Klaus-Dieter Lang
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Publication number: 20180088162Abstract: An apparatus and a method for determining an antenna characteristic of an antenna under test in free space is disclosed. Measurement results of a transmitted power of a measurement signal transmitted between the reference antenna and an antenna under test are detected, wherein detecting takes place in the frequency domain. The detected measurement results are transformed into the time domain and a time-domain filter is applied to the measurement results converted into the time domain. A filter width of the time-domain filter is determined in dependence on a spatial distance between the reference antenna and the antenna under test. Measurement result portions that result due to a multipath propagation of the measurement signal between the reference antenna and the antenna under test are reduced or removed.Type: ApplicationFiled: September 29, 2017Publication date: March 29, 2018Applicants: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V., Technische Universitaet BerlinInventors: Ivan Ndip, Volker Grosser, Christian Tschoban, Brian Curran, Max Huhn, Klaus-Dieter Lang
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Patent number: 9430235Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.Type: GrantFiled: July 29, 2013Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Khary J. Alexander, Brian Curran, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell, Brian R. Prasky, Brian W. Thompto
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Patent number: 9135005Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.Type: GrantFiled: January 28, 2010Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, James R. Mitchell
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Patent number: 9104399Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.Type: GrantFiled: December 23, 2009Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
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Publication number: 20150051957Abstract: A disclosed method includes determining a customer experience value (CXV) of an entity by a server computer. The CXV may be determined by calculating a customer acquisition value of the entity, calculating a customer retention value of the entity, and calculating an operation efficiency value of the entity. The customer acquisition value may be based on at least one of a measure of acquisition performance of the entity or a measure of operational performance of the entity. The customer retention value may be based on at least one of a measure of customer retention or a measure of service quality. The operation efficiency value may be based on at least one of a measure of operating costs of the entity or a measure of strategic costs of the entity. The method includes using, by a customer relationship management application, the determined CXV to indicate a measure of customer satisfaction.Type: ApplicationFiled: August 15, 2013Publication date: February 19, 2015Applicant: Oracle International CorporationInventors: Jeffrey Griebeler, Brian Curran
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Patent number: 8645669Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.Type: GrantFiled: May 5, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi
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Publication number: 20130318330Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. ALEXANDER, Khary J. ALEXANDER, Brian CURRAN, Jonathan T. HSIEH, Christian JACOBI, James R. MITCHELL, Brian R. PRASKY, Brian W. THOMPTO
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Patent number: 8521992Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.Type: GrantFiled: June 24, 2010Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Khary J. Alexander, Brian Curran, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell, Brian R. Prasky, Brian W. Thompto
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Patent number: 8495341Abstract: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.Type: GrantFiled: February 17, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, Wen Li
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Patent number: 8468325Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.Type: GrantFiled: December 22, 2009Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Khary J. Alexander, Brian Curran, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell, Brian R. Prasky, Brian W. Thompto
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Patent number: 8464030Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.Type: GrantFiled: April 9, 2010Date of Patent: June 11, 2013Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Lee Eisen, Bruce Giamei, David Hutton
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Publication number: 20110276764Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.Type: ApplicationFiled: May 5, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi