Abstract: In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.

Abstract: A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

Abstract: A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet including the header and the header CRC; (4) loading a timer to run until data required to complete the command is received or the timer expires; and (5) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

Abstract: A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a variable gap; and (3) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

Abstract: In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

Abstract: A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline.

Abstract: A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.