Abstract: Embodiments of an amplifier system with enhanced load-driving capability are disclosed. The amplifier system comprises a main amplifier and multiple parallel output stages. Each additional output stage receives a current signal proportional to the main amplifier output current and outputs the replica of the main amplifier output current. An amplifier control circuit in the main amplifier receives current signals representing the current of each additional output stage to set a quiescent current of the amplifier system accordingly to ensure stability while minimizing quiescent power dissipation. Advantages of the amplifier system embodiments include unlimited load driving capability in principle, greatly relieved burden on thermal management, cost-effectiveness, design flexibility over single chip solutions, controllable current biasing of each output stage attached to the system, and controllable quiescent power dissipation based on application.

Abstract: High-voltage (HV) semiconductor switches are used in various applications. On-impedance (Ron) of the HV switches is prone to process, voltage, and temperature (PVT) variations. The present invention discloses system and method embodiments to calibrate a gate-to-source voltage (Vgs) of the switch based on a low temperature coefficient resistor and current references. The Ron of a replica switch transistor is matched to a reference resistor using a feedback to generate the required Vgs voltage. The calibrated Vgs is enforced to the floating HV switch transistor via controlling the bias current of a replica gate driver by feedback. With this approach, a desired input current to the gate driver may be obtained and applied to a main gate driver to control the Ron of the floating HV switches. Simulation results demonstrate a significant improvement in Ron variation.

Abstract: A low input capacitance input stage for a high voltage amplifier includes a first input transistor configured to receive a first portion of a differential input signal and provide a first portion of an output signal, and a second input transistor configured to receive a second portion of the differential input signal and provide a second portion of the output signal. The amplifier can include a degeneration stage with a bias generator circuit. The degeneration stage can include first and second degeneration transistors coupled in series. The bias generator circuit can provide respective first and second bias signals to gate terminals of the first and second degeneration transistors to control an impedance of a signal path that couples source terminals of the first and second input transistors.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: In an optical detection system, features of interest can be identified from ADC circuitry data prior to inter-circuit communication with downstream object or target processing circuitry. In this manner, a volume of data being transferred to such downstream processing circuitry can be reduced as compared to other approaches, simplifying the receive signal processing chain and providing power savings. First-tier signal processing circuitry to identify features of interest can be located on or within a commonly-shared integrated circuit package with ADC circuitry, and downstream processing circuitry for object processing or range estimation can be fed with a data link meeting less stringent requirements than a link between the ADC circuitry and first-tier signal processing circuitry.

Abstract: A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.

Abstract: In an optical detection system, features of interest can be identified from ADC circuitry data prior to inter-circuit communication with downstream object or target processing circuitry. In this manner, a volume of data being transferred to such downstream processing circuitry can be reduced as compared to other approaches, simplifying the receive signal processing chain and providing power savings.

Abstract: A semiconductor wafer in an intermediate stage of fabrication having an array of slices. All but one of the slices may have integrated circuit components interconnected by metallization layers to form a die having an operable circuit, with the remaining slice functioning as a scribe area or line. Two embodiments of slices are disclosed in which one slice is a rectangle of a minimum width to function as a scribe area, and the other slice is composed of a sliver and a rectangle with the latter also having a minimum width to function as a scribe area. Each embodiment of a slice can be extended lengthwise with an extension box that also can function to contain operative components or function as a scribe area.