Patents by Inventor Brian D. Hansen

Brian D. Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10625280
    Abstract: Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for scanning the microelectronic substrate through a cryogenic fluid mixture used to treat an exposed surface of the microelectronic substrate. In particular, an improved nozzle design used to expand the fluid mixture is disclosed herein. In one embodiment, the nozzle design incorporates a two nozzle pieces are combined to form a single nozzle design, in which the two pieces are slight misaligned to form a unique orifice design. In another embodiment, two pieces are combined and aligned along a common axis of the fluid conduit. However, an offset piece is inserted between the two pieces and has a hole that misaligned from the flow conduits of the two other pieces.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 21, 2020
    Assignee: TEL FSI, INC.
    Inventors: Edward D. Hanzlik, Brian D. Hansen
  • Patent number: 10418270
    Abstract: A wafer edge lift pin of an apparatus for manufacturing a semiconductor device is described. The wafer edge lift pin includes an offset top section containing a notch portion to support and laterally confine the wafer. The notch portion horizontally sweeps away from the wafer along a radius so that rotation adjusts lateral confinement of the wafer. A base section below the top section has a diameter greater than a diameter of the top section across the notch portion to help strengthen the pin and to allow perpendicular mounting. A bottom section has a diameter that is smaller than the diameter of the base section and provides a boss feature to mount the lift pin. The apparatus includes a process chamber where the wafer is processed, a chuck assembly on which the wafer is loaded. At least three wafer edge lift pins move the wafer up and down.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 17, 2019
    Assignee: TEL FSI, INC.
    Inventors: Edward D. Hanzlik, Sean Moore, Brian D. Hansen