Abstract: A method and apparatus for eliminating unnecessary address transitions on an DRAM address bus and DRAM write enable line. In a known DRAM controller and DRAM array, all address transitions on the CPU address bus are mirrored by address transitions on the DRAM address bus. The present invention eliminates all address transitions not associated with an actual DRAM access cycle by eliminating the DRAM controller's address multiplexer and replacing it with a multiplexing driver circuit and a bus holder circuit. In a similar fashion, a DRAM write enable circuit eliminates all transitions on the DRAM write enable line that are not associated with actual DRAM access cycles. Although specifically discussed in terms of a DRAM array and its associated circuitry, the portion of the present invention that reduces address transitions on the DRAM address lines could be used in any device currently using a multiplexer.

Abstract: A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral access, a display system, a single memory system for storing multiple frame buffers, data buses for transferring image information and a video controller for processing the image information received and for converting CPU addresses into memory addresses for accessing the memory system. The multiple frame buffers stored in the memory system in accordance with the present invention provide either overlay images for a display or separate images for separate displays or both.

Abstract: A computer having a video circuit which is configured by a monitor identification signal is described. The self-configuring circuit permits connection to a variety of monitor types without the need for a separate video card or other dedicated circuitry compatible with the specific monitor type. The computer automatically senses the type of the monitor to which it is coupled, then configures its internal circuitry to provide compatible video signals to the monitor. The invented computer includes a central processing unit (CPU) for executing a program to provide video data for display on the monitor. The data is stored in the computer in a random-access memory (RAM). The monitor provides an identification signal to the video circuit which then provides both the appropriate video timing signals and the video data to the monitor for display thereon. The identification signal is used to configure the video circuitry in accordance with the requirements of the monitor.

Abstract: A computer which provides a video signal for display is disclosed. The computer has a central processing unit (CPU) which executes a program to provide video data for a display which is organized as a matrix of pixel elements, each pixel element being represented by a certain number of bits of video data stored within a random-access memory (RAM) in the computer. A video integrated circuit is coupled to the RAM to provide N bits of video data per pixel to the display at a dot clock rate consistent with the requirements of the display. This video circuit, rather than having its own video RAM, shares the system memory (i.e., RAM) with the CPU. A memory controller arbitrates access to the RAM between the CPU and the video circuit in a manner that denies access to the RAM by the CPU whenever the video circuit is reading video data from the RAM.