Abstract: A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers.

Abstract: A cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests initiated by a microprocessor connected to the cache are stored into the non-prefetch ways. Accessed cache lines are thereby maintained within the cache separately from prefetch cache lines. When a prefetch cache line is presented to the cache for storage, the prefetch cache line may displace another prefetch cache line but does not displace an accessed cache line. A cache hit in either the prefetch way or the non-prefetch ways causes the cache line to be delivered to the requesting microprocessor in a cache hit fashion. The cache is further configured to move prefetch cache lines from the prefetch way to the non-prefetch way if the prefetch cache lines are requested (i.e. they become accessed cache lines).

Abstract: A main memory comprises one or more memory devices which include logic for performing a predetermined graphics operation upon graphics primitives stored therein. The microprocessor(s) within the computer system may direct the memory to perform the predetermined operation upon the graphics primitives instead of performing the operation within the microprocessor(s). If the graphics primitives are stored into multiple memory devices, each memory device operates upon the graphics primitives stored within that memory device in parallel with the other memory device's operation. Accordingly, the bandwidth is a linear factor of the number of memory devices storing graphics primitives. In one embodiment, each memory device iteratively performs the predetermined operation upon the set of graphics primitives stored in that memory device. Because the memory device is iterative, logic for performing the predetermined graphics operation upon one graphics primitive at a time may be employed.

Abstract: A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

Abstract: A microprocessor includes an expanded set of registers in addition to the architected set of registers specified by the microprocessor architecture employed by the microprocessor. The expanded set of registers are memory-mapped within the context of the program being executed. Upon a context switch, the microprocessor saves the state of the expanded registers to the corresponding memory locations. An application program may make use of the expanded registers by assigning the most-often used operands in the program to the set of memory locations corresponding to the expanded registers. The application programmer may than code instructions which access these operands with register identifiers corresponding to the expanded registers. In one embodiment, the microprocessor implements a portion of the expanded registers instead of the entire set of expanded registers.

Abstract: A superscalar processor provides register renaming using a reorder buffer includes special registers for handling predefined special instructions that operate on an odd-width data word. The superscalar processor includes a reorder buffer which stores result data having a predetermined standard bit-width. One or more instructions that generally occur only occasionally have a result data width that is substantially larger than the standard bit-width. The reorder buffer stores data of the standard bit-width and the occasional large bit-width in a storage that includes a plurality of standard-width storage elements in a first-in-first-out FIFO reorder buffer queue and a separate buffer that is specifically allocated for storing an extended result element. An extended result element includes a portion of a large bit-width result in excess of the standard bit-width result size.

Abstract: A hardware simulation system is disclosed which includes a high frequency clock which is gated with a system clock to produce a high frequency enabled clock. The high frequency enabled clock is used to clock an edge triggered latch within the hardware simulation system. Thus, the system advantageously emulates level sensitive latches using edge triggered latches.

Abstract: A read line for a column of memory cells within an array is divided into a first read line segment, a first read buffer, and a second read line segment. Both the first and second read line segments occupy a single wiring channel. When reading a memory cell connected to the first read line segment, the level of the first read line segment is sensed by the first read buffer and conveyed to a column read output node by way of the second read line segment and an associated second read buffer. Alternatively, when reading a memory cell connected to the second read line segment, the first read buffer is disabled, thus adopting a high impedance output, and the level of the second read line segment is sensed by the second read buffer and conveyed to the column read output node. Each of the first and second read line segments have less capacitive loading than a single read line, which results in lower power and faster read access times.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain to be compared with respect to one another. The delay chain is employed within a clock generator circuit that generates internal clock signals of a microprocessor. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. During a test operation when it is desired to test the variable delay units for possible defects, the four delay units are electrically separated from one another by setting the multiplexers in a test mode. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: An apparatus which has storage cells arrayed in a matrix having rows and columns. The apparatus includes row select lines for effecting selection of a first array of the storage cells, and column designation lines for effecting selection of at least one specific storage cell among the selected first array of storage cells. Read lines for enabling reading of the contents of the various storage cells are included, as well as an interface circuit associated with each storage cell for effecting operative connection of respective storage cells to appropriate respective read lines. The interface circuits are selectively operatively connected to the row select lines and the column designation lines according to a predetermined arrangement.

Abstract: There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.

Abstract: A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control.