Patents by Inventor Brian D. Pfeifer
Brian D. Pfeifer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971411Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.Type: GrantFiled: October 8, 2018Date of Patent: April 6, 2021Assignee: TEL Epion Inc.Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
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Publication number: 20190043766Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.Type: ApplicationFiled: October 8, 2018Publication date: February 7, 2019Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
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Patent number: 10096527Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.Type: GrantFiled: August 19, 2016Date of Patent: October 9, 2018Assignee: TEL Epion Inc.Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
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Publication number: 20170053843Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.Type: ApplicationFiled: August 19, 2016Publication date: February 23, 2017Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
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Patent number: 7584077Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: GrantFiled: June 18, 2004Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Patent number: 6823496Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: GrantFiled: April 23, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20040221250Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: June 18, 2004Publication date: November 4, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20030200513Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox
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Patent number: 6455434Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.Type: GrantFiled: October 23, 2001Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Chad R. Binkerd, Jose L. Cruz, Timothy C. Krywanczyk, Brian D. Pfeifer, Rosemary A. Previti-Kelly, Patricia Schink, Amye L. Wells