Patents by Inventor Brian D. Pfeifer

Brian D. Pfeifer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971411
    Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 6, 2021
    Assignee: TEL Epion Inc.
    Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
  • Publication number: 20190043766
    Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
  • Patent number: 10096527
    Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 9, 2018
    Assignee: TEL Epion Inc.
    Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
  • Publication number: 20170053843
    Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 23, 2017
    Inventors: Joshua LaRose, Brian D. Pfeifer, Vincent Lagana-Gizzo, Noel Russell
  • Patent number: 7584077
    Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
  • Patent number: 6823496
    Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
  • Publication number: 20040221250
    Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
    Type: Application
    Filed: June 18, 2004
    Publication date: November 4, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
  • Publication number: 20030200513
    Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 23, 2003
    Applicant: International Business Machines Corporation
    Inventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox
  • Patent number: 6455434
    Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chad R. Binkerd, Jose L. Cruz, Timothy C. Krywanczyk, Brian D. Pfeifer, Rosemary A. Previti-Kelly, Patricia Schink, Amye L. Wells