Abstract: A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a device with a textured surface having multiple grooves in an otherwise relatively flat surface. The textured surface of the heat management device is designed, in conjunction with a thermal interface material (TIM), to push gas bubbles out of the flat areas such that the gas bubbles are trapped in the grooves or driven out of the interface between the device and the TIM altogether. The area of the grooves is small relative to the ungrooved areas (i.e., the flat areas), such that when the gas bubbles are trapped in the grooved areas, the ungrooved areas work even better for heat transfer. With the area of the regions for the flat portions being substantially greater than the area of the regions for the grooves, the textured heat management device is designed to lower thermal resistance, increase thermal conductivity, and increase heat transfer from one or more IC dies to a heat sink assembly in an IC package.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a carry generation portion and a sum generation portion. The carry generation portion is configured to generate a first carry signal from a second set of three input signals. The sum generation portion is configured to generate a second sum signal from the first sum signal and the first carry signal. The carry chain logic is configured to process the first sum signal, the second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal.

Abstract: A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.

Abstract: A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.