Patents by Inventor Brian D. Pratt

Brian D. Pratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7772086
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: August 10, 2010
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Patent number: 7759204
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: July 20, 2010
    Assignee: Third Dimension Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Publication number: 20080290442
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Application
    Filed: April 16, 2008
    Publication date: November 27, 2008
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Publication number: 20080283956
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Application
    Filed: April 16, 2008
    Publication date: November 20, 2008
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Publication number: 20080164521
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 10, 2008
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Publication number: 20080166855
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Application
    Filed: March 21, 2008
    Publication date: July 10, 2008
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Patent number: 7364994
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 29, 2008
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Brian D. Pratt
  • Patent number: 7354818
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches are formed in the termination region. The trenches of the second plurality of trenches are filled with the dielectric material.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: April 8, 2008
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Patent number: 7052982
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: May 30, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Brian D. Pratt
  • Patent number: 6977203
    Abstract: A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: December 20, 2005
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Brian D. Pratt
  • Patent number: 6645815
    Abstract: A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 11, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Brian D. Pratt
  • Publication number: 20030096479
    Abstract: A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
    Type: Application
    Filed: November 20, 2001
    Publication date: May 22, 2003
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Brian D. Pratt
  • Publication number: 20030096480
    Abstract: A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device.
    Type: Application
    Filed: November 20, 2001
    Publication date: May 22, 2003
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Brian D. Pratt