Patents by Inventor Brian D. Schultz

Brian D. Schultz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622447
    Abstract: A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 14, 2020
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Theodore D. Kennedy, Amanda Kerr, William E. Hoke
  • Publication number: 20190262201
    Abstract: A patient support apparatus may include a support surface configured to conduct air along a top face of the support surface so that heat and moisture from a patient lying on the support surface are drawn away from the top face of the support surface. An opening may be formed in a side of the support surface. A cavity may extend from the opening into the support surface. An inlet port may be positioned within the cavity and fluidly coupled to the top face. A blower assembly may be configured to position within the cavity. The blower assembly may have an outlet port that couples to the inlet port when the blower assembly is positioned within the cavity. The blower assembly may conduct air through the inlet port to the top face of the support surface.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventors: Darrell L. Borgman, Douglas E. Borgman, Arpit Shah, Wui Hsien Wong, Keith Moores, Jason M. Gilreath, Michael R. Montini, Charles A. Lachenbruch, Eric R. Meyer, Frank E. Sauser, Catherine M. Wagner, Rachel L. Williamson, Brandon P. Fisk, Jason B. Grace, Brian Guthrie, Nicole Johannigman, Gregory J. Shannon, David C. Newkirk, Michael Churilla, Jnanesha Ramegowda, Taylor Franklin, Kathryn R. Smith, John G. Byers, Frederick K. Schultz, Andrew R. Wager, Sridhar Karimpuzha Seshadri, Gary R. Gibbons, Scott M. Corbin, John Goewert, Thomas L. Simpson, Faron L. Blessing, James D. Voll, Kin Meng Choi, Stephen S. Amrhein, Herve Gautier, Jean-Francois Lellig, Philippe Kaikenger, Matthieu Guetta
  • Patent number: 10276705
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 30, 2019
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Publication number: 20180286954
    Abstract: A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Raytheon Company
    Inventors: Brian D. Schultz, Theodore D. Kennedy, Amanda Kerr, William E. Hoke
  • Publication number: 20180204940
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Applicant: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Patent number: 9960262
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 1, 2018
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Publication number: 20170250273
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Applicant: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Patent number: 9419125
    Abstract: A semiconductor structure having a Group III-N buffer layer and a Group III-N barrier layer in direct contact to form a junction between the Group III-V buffer layer the Group III-N barrier layer producing a two dimensional electron gas (2DEG) channel, the Group III-N barrier layer having a varying dopant concentration. The lower region of the Group III-N barrier layer closest to the junction is void of intentionally introduced dopant and a region above the lower region having intentionally introduced, predetermined dopant with a predetermined doping concentration above 1×1017 atoms per cm3.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 16, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Brian D. Schultz, Abbas Torabi, Eduardo M. Chumbes, Shahed Reza, William E. Hoke
  • Patent number: 9414478
    Abstract: A plasma generating system. A pair of electrodes are spaced apart by an electrode gap. A source of a gas adapted to place the gas in the electrode gap. A power generating circuit is coupled to the electrodes to generate an electric field across the electrodes so as to initiate a plasma discharge within the electrode gap. The power generating circuit has adequate capacity to maintain a sufficient electric field across the gap during the plasma discharge to allow a plasma impedance to self-tune to the plasma generating system. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL TECHNOLOGY CENTER
    Inventors: Brian D. Schultz, William M. Hooke, Michael J. Kelly
  • Publication number: 20140197732
    Abstract: A plasma generating system. A pair of electrodes are spaced apart by an electrode gap. A source of a gas adapted to place the gas in the electrode gap. A power generating circuit is coupled to the electrodes to generate an electric field across the electrodes so as to initiate a plasma discharge within the electrode gap. The power generating circuit has adequate capacity to maintain a sufficient electric field across the gap during the plasma discharge to allow a plasma impedance to self-tune to the plasma generating system. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: December 4, 2013
    Publication date: July 17, 2014
    Applicant: INTERNATIONAL TECHNOLOGY CENTER
    Inventors: Brian D. Schultz, William M. Hooke, Michael J. Kelly
  • Patent number: 8263976
    Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: September 11, 2012
    Assignee: International Technology Center
    Inventors: Brian D. Schultz, Gary Elder McGuire
  • Publication number: 20110210373
    Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 1, 2011
    Inventors: Brian D. Schultz, Gary Elder McGuire
  • Patent number: 7960259
    Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 14, 2011
    Assignee: International Technology Center
    Inventors: Brian D. Schultz, Gary Elder McGuire
  • Publication number: 20090079040
    Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 26, 2009
    Inventors: Brian D. Schultz, Gary Elder McGuire