Patents by Inventor Brian D. Young

Brian D. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160314502
    Abstract: A tool provides for the batch processing of multiple ad units, allowing quickly and simultaneously reformatting assets into multiple standard online advertisement formats and exporting the ad units to an ad server with scripting code so as to save time and cost in generating an online advertising campaign. The tool may also include high level commands to allow a user to simultaneously or individually adjust an ad unit for different renderings for an online advertising campaign.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: Andrew Lindsay, Noel Maguigad, Marin Petkov, Shatay Zoe Trigere, Brian D. Young
  • Patent number: 9377504
    Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stanley A. Cejka, Steven A. Atherton, William J. Downey, James C. Golab, Brian D. Young
  • Publication number: 20160110900
    Abstract: The system and method for providing a composite image corresponding to a textual message. The composite image is generated by receiving a text message, parsing out styling information, using predetermined size and spacing for combinations of typographical characters in combinations with a graphics editing routine which allows for the recognition and translation of text into a series of images which can then be presented to a viewer as a composite image.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 21, 2016
    Inventors: Mateen Moosa, Marin Petkov, Andrew Lindsay, Brian D. Young
  • Publication number: 20150276854
    Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stanley A. Cejka, Steven A. Atherton, William J. Downey, James C. Gobab, Brian D. Young
  • Patent number: 8872338
    Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Brian D. Young
  • Publication number: 20140131866
    Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Inventor: Brian D. Young
  • Patent number: 7598772
    Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: October 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Brian D. Young
  • Publication number: 20080157843
    Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.
    Type: Application
    Filed: July 5, 2007
    Publication date: July 3, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Brian D. Young
  • Publication number: 20030201802
    Abstract: A transmission circuit (150) provides two outputs. The two outputs carry both signal information as a differential voltage and carry a signal as a common mode voltage. The differential voltage is sensed by a comparator. The common mode voltage is sensed by a single-ended amplifier. This transmission circuit is combined with another one so that the signal, which is carried as the common mode signal, is carried on the first pair of differential signals as well as a second pair of differential signals. Thus, one signal is carried as a differential signal on two lines, a third signal is carried as a differential signal on two additional lines, and the common mode signal is carried on all four lines. The first two lines provide the differential signal which is sensed by a comparator. The second pair of lines carries a differential signal which is sensed by another comparator. The first pair of lines is combined to provide a common mode signal.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 30, 2003
    Inventor: Brian D. Young
  • Patent number: 6346832
    Abstract: A transmission circuit provides two outputs. The two outputs carry both signal information as a differential voltage and carry a signal as a common mode voltage. The differential voltage is sensed by a comparator. The common mode voltage is sensed by a single-ended amplifier. This transmission circuit is combined with another one so that the signal, which is carried as the common mode signal, is carried on the first pair of differential signals as well as a second pair of differential signals. Thus, one signal is carried as a differential signal on two lines, a third signal is carried as a differential signal on two additional lines, and the common mode signal is carried on all four lines. The first two lines provide the differential signal which is sensed by a comparator. The second pair of lines carries a differential signal which is sensed by another comparator. The first pair of lines is combined to provide a common mode signal.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: February 12, 2002
    Assignee: Motorola, Inc.
    Inventor: Brian D. Young
  • Patent number: 5724727
    Abstract: An electronic component (15) such as a printed circuit board (PCB) is formed using a sintering process. A layer of dielectric powder (11) is partially converted to a solid layer of dielectric material (14) by exposing selective portions of the powder (11) to a laser (17). A layer of conductive powder (20) is then formed over the solid layer of dielectric material (14) and selectively sintered to form a solid layer of conductive material (19). This process can be used to form an interconnect structure (45), a coaxial structure (60), a cavity (89), a trench structure (90), or a slug (91), conductive traces (19), bond pads (31), or any other circuit board structure.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: March 10, 1998
    Assignee: Motorola, Inc.
    Inventors: Mona A. Chopra, Everitt W. Mace, Brian D. Young
  • Patent number: 5657033
    Abstract: A microwave horn antenna structure including a plurality of planar dielectric insulating layers stacked in laminar fashion so as to have a bottom layer and a top layer, respective similarly shaped conductive trace loops co-axially disposed on a plurality of contiguous ones of the insulating layers and of incrementally increasing size from a lowermost conductive trace loop an uppermost conductive trace loop, and a plurality of conductive vias extending through the planar dielectric layers for electrically interconnecting the respective conductive trace loops. Also disclosed is a flared notch antenna that includes a plurality of planar dielectric insulating layers stacked in laminar fashion, a slanted column of electrically interconnected conductive vias formed in a plurality of contiguous ones of the dielectric insulating layers and a second slanted column of electrically interconnected conductive vias formed in the contiguous ones of the dielectric insulating layers.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Hughes Electronics
    Inventor: Brian D. Young
  • Patent number: 5498905
    Abstract: A unitized multilayer circuit structure that includes a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides formed by edges of the dielectric insulating layers and recessed regions formed in one or more one sides of the substrate for use in attaching the unitized multilayer circuit structure to a higher level assembly or for attaching electrical contact circuitry to the unitized multilayer circuit structure.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: March 12, 1996
    Assignee: Hughes Aircraft Company
    Inventor: Brian D. Young
  • Patent number: 5453750
    Abstract: A multistage transmission line interconnect device (50) for joining two microstrip circuits (82, 86). A center conductor pin (52) extends through a cylindrical dielectric (54) to form a coaxial midsection of the device. The ends of the pin extend from the dielectric to form a conductor for a straight open troughline at each end of the device. The ends of the pin are connected to the microstrip circuits by ribbon bonds (80, 84). Because the midsection of the device is coaxial, the microstrip circuits (82, 86) may be oriented at arbitrary angles with respect to one another.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: September 26, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Daniel M. Battista, Clifton Quan, Keith Whaley, Bruce F. Wolfe, Brian D. Young
  • Patent number: 5429859
    Abstract: A unitized multilayer circuit structure including a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides, and at least one alignment groove formed in one side of the substrate.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: July 4, 1995
    Assignee: Hughes Aircraft Company
    Inventor: Brian D. Young
  • Patent number: 5408053
    Abstract: A transmission line structure including a central signal conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers of a unitized multilayer circuit structure, a first ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from one side of the central signal conductor stack, and a second ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from another side of the central signal conductor stack such that the central conductor stack is laterally between the first and second ground conductor stacks.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: April 18, 1995
    Assignee: Hughes Aircraft Company
    Inventor: Brian D. Young
  • Patent number: 4942203
    Abstract: A polymer composition comprising (1) a polyether polyol which is a product obtained by the free radical addition of a fluoro-olefin of the general formula: ##STR1## wherein Y represents F or fluoroalkyl and Z represents Cl or F(CF.sub.2)m--wherein m is an integer from 0 to 10 or Y and Z together form a (CH.sub.2)p--chain wherein p represents an integer from 2 to 4, to a polytetramethylene gylcol having a molecular weight in the range 162 to 5000 and (2) at least one acrylic polymer. The composition is useful for coating compositions or for the fabrication of films.
    Type: Grant
    Filed: July 11, 1988
    Date of Patent: July 17, 1990
    Assignee: Imperial Chemical Industries PlC
    Inventors: John N. Conti-Ramsden, Robert A. Head, Richard L. Powell, Brian D. Young
  • Patent number: 4877839
    Abstract: Composition, optionally curable, comprising a fluorocopolymer admixed with an acrylic polymer, where the fluoropolymer comprises units of a fluorolefine (e.g. TFE) and fluoroallylether (e.g. tetrafluororallylether).
    Type: Grant
    Filed: June 8, 1988
    Date of Patent: October 31, 1989
    Assignee: Imperial Chemical Industries PLC
    Inventors: John N. Conti-Ramsden, Richard L. Powell, Brian D. Young, Jeffrey Farrar, Debra K. Brown