Patents by Inventor Brian David Allison
Brian David Allison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8001354Abstract: A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.Type: GrantFiled: April 27, 2007Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7882314Abstract: A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.Type: GrantFiled: September 7, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7882323Abstract: A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.Type: GrantFiled: September 7, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7761669Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.Type: GrantFiled: July 10, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
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Publication number: 20090216959Abstract: The present invention is generally directed to a method, system, and program product wherein at least one command in a first queue is transferred to a second queue. When the first queue can no longer accept command(s) and a second queue is able to accept command(s), the second queue accepts the command(s) that the first queue can not. When the first queue is able to accept command(s), and there are command(s) in the second memory port that should have been in the first queue, the command(s) in the second queue are transferred to the first queue.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Inventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20090216960Abstract: The present invention is generally directed to a method, system, and program product wherein at least two memory ports associated within a memory controller are capable of transferring commands between one another in unbalanced memory configurations. When the first memory port can no longer accept commands and a second memory port is able to accept commands, the second memory port accepts the commands that the first memory port can not. When the first memory port is able to accept commands, and there are commands in the second memory port that should have been in the first memory port, the commands in the second memory port are transferred to the first memory port.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Inventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20090070647Abstract: A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.Type: ApplicationFiled: September 7, 2007Publication date: March 12, 2009Inventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20090070648Abstract: A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.Type: ApplicationFiled: September 7, 2007Publication date: March 12, 2009Inventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20090019239Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
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Publication number: 20090019238Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes fuller, requests are serviced in a manner that maximizes throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
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Publication number: 20080271054Abstract: A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Inventors: Brian David Allison, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 6615334Abstract: A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.Type: GrantFiled: December 27, 2000Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Brian David Allison, Scott D. Clark
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Patent number: 6467033Abstract: A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.Type: GrantFiled: December 12, 2000Date of Patent: October 15, 2002Assignee: International Business Machines CorporationInventors: Brian David Allison, Scott D. Clark, Joseph A. Kirscht
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Publication number: 20020083294Abstract: A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.Type: ApplicationFiled: December 27, 2000Publication date: June 27, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian David Allison, Scott D. Clark
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Publication number: 20020073287Abstract: A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.Type: ApplicationFiled: December 12, 2000Publication date: June 13, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian David Allison, Scott D. Clark, Joseph A. Kirscht