Abstract: Some embodiments are associated with an input signal comprising a first and a second photon event incident on a photon-counting semiconductor detector. A relatively slow charge collection shaping amplifier may receive the input signal and output an indication of a total amount of energy associated with the superposition of the first and second events. A relatively fast charge collection shaping amplifier may receive the input signal and output an indication that is used to allocate a first portion of the total amount of energy to the first event and a second portion of the total amount of energy to the second event.

Abstract: A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample.

Abstract: Some embodiments are associated with an X-ray source configured to generate X-rays directed toward an object, wherein the X-ray source is to: (i) generate a first energy X-ray pulse, (ii) switch to generate a second energy X-ray pulse, and (iii) switch back to generate another first energy X-ray pulse. A detector may be associated with multiple image pixels, and the detector includes, for each pixel: an X-ray sensitive element to receive X-rays; a first storage element and associated switch to capture information associated with the first energy X-ray pulses; and a second storage element and associated switch to capture information associated with the second energy X-ray pulse. A controller may synchronize the X-ray source and detector.

Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines—selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.

Abstract: An imager including sub-imager pixel arrays having a plurality of four-side buttable imagers distributed on a substrate and an on-chip digitizing readout circuit. Pixel groupings formed from among the plurality of four-side buttable imagers. The readout electronics including a buffer amplifier for each of the pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping. A plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings. An analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a fully addressable input selection to individually select an output from each of the plurality of shared analog front ends. An output of the analog-to-digital converter connected to a trace on a back surface of the wafer substrate by a through-substrate-via.

Abstract: An imager including sub-imager pixel arrays having a plurality of four-side buttable imagers distributed on a substrate and an on-chip digitizing readout circuit. Pixel groupings formed from among the plurality of four-side buttable imagers. The readout electronics including a buffer amplifier for each of the pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping. A plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings. An analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a fully addressable input selection to individually select an output from each of the plurality of shared analog front ends. An output of the analog-to-digital converter connected to a trace on a back surface of the wafer substrate by a through-substrate-via.

Abstract: A pixelated gamma detector includes a scintillator column assembly having scintillator crystals and optical transparent elements alternating along a longitudinal axis, a collimator assembly having longitudinal walls separated by collimator septum, the collimator septum spaced apart to form collimator channels, the scintillator column assembly positioned adjacent to the collimator assembly so that the respective ones of the scintillator crystal are positioned adjacent to respective ones of the collimator channels, the respective ones of the optical transparent element are positioned adjacent to respective ones of the collimator septum, and a first photosensor and a second photosensor, the first and the second photosensor each connected to an opposing end of the scintillator column assembly. A system and a method for inspecting and/or detecting defects in an interior of an object are also disclosed.

Abstract: A digital X-ray detector is provided. The digital X-ray detector includes multiple pixels, each pixel including a pinned photodiode, and multiple readout channels coupled to each pinned photodiode, wherein each readout channel includes at least one charge-storage capacitor, an amplifier, and a transfer gate. The digital X-ray detector also includes control circuitry coupled to each pixel of the multiple pixels and configured to selectively control a flow of photocharge generated by each pinned photodiode to a respective at least one charge-storage capacitor of each respective readout channel via control of each respective transfer gate of each respective readout channel.

Abstract: A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample.

Abstract: A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample.

Abstract: A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample.

Abstract: A system and method for generating a digital image in fluorescence gel imaging is disclosed. The method includes providing a gel sample and placing the gel sample on a flat panel detector having array of photodiodes and transistors that collect light generated from the gel sample. The gel sample is illuminated using a light source integrated into the flat panel imaging system and light emitted by the gel sample responsive to an excitation of the gel sample by light provided by the light source is then collected, with the light emitted by the gel sample being collected by the array of photodiodes of the flat panel detector and converted to electric charges to generate light data. The light data is then processed to generate a digital image of the gel sample.

Abstract: A collimator grid and a method of fabricating the collimator grid are disclosed. The method includes molding a plurality of plates, each plate includes a plurality of grooves in a first surface, a plurality of fin tips in a second surface disposed opposite to the first surface, plurality of ribs on a first pair of peripheral sides, a plurality of first fiducials formed on the plurality of ribs, and a plurality of second fiducials formed on a second pair of peripheral sides. The method includes machining the second surface to form the plurality of fins having predefined dimensions. Further, the method includes stacking the plurality of plates overlapping each other based on the plurality of first fiducials, and machining the plurality of ribs and first fiducials to form the collimator grid.

Abstract: A collimator grid and a method of fabricating the collimator grid are disclosed. The method includes molding a plurality of plates, each plate includes a plurality of grooves in a first surface, a plurality of fin tips in a second surface disposed opposite to the first surface, plurality of ribs on a first pair of peripheral sides, a plurality of first fiducials formed on the plurality of ribs, and a plurality of second fiducials formed on a second pair of peripheral sides. The method includes machining the second surface to form the plurality of fins having predefined dimensions. Further, the method includes stacking the plurality of plates overlapping each other based on the plurality of first fiducials, and machining the plurality of ribs and first fiducials to form the collimator grid.

Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

Abstract: An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.

Abstract: An electronic assembly is provided. The assembly comprises a substrate having a plurality of conductive contacts disposed on a surface of the substrate. The substrate comprises a dielectric material. The assembly comprises a detector having a plurality of conductive contacts disposed on a surface of the detector which is adjacent to the surface of the substrate. At least one compliant interconnect is disposed between the substrate and the detector. The conductive contacts of the substrate and the conductive contacts of the detector are in electrical communication with the compliant interconnect via a conductive epoxy. The compliant interconnect comprises a polymer core having an electrically conductive outer surface. In certain embodiments, the assembly comprises an interposer. In certain embodiments, an under-fill is disposed between the surface of the substrate and the surface of the detector.

Abstract: An imaging detection system includes at least one location detection device configured to determine coordinates of a target, at least one detector configured to detect events from a source associated with the target, and a processor coupled in communication with the at least one location detection device and the at least one detector. The processor is configured to receive the coordinates from the at least one location detection device and the events from the at least one detector, translate the events using the coordinates acquired from the at least one location detection device to compensate for a relative motion between the source and the at least one detector, and output a processed data set having the events translated based on the coordinates.

Abstract: An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers.