Patents by Inventor Brian Donald Gerson

Brian Donald Gerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5905386
    Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: May 18, 1999
    Assignee: PMC-Sierra Ltd.
    Inventor: Brian Donald Gerson
  • Patent number: 5835501
    Abstract: A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: November 10, 1998
    Assignee: PMC-Sierra Ltd.
    Inventors: Kamal Dalmia, Andre Ivanov, Brian Donald Gerson, Curtis Lapadat
  • Patent number: 5793225
    Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
    Type: Grant
    Filed: January 2, 1996
    Date of Patent: August 11, 1998
    Assignee: PMC-Sierra, Inc.
    Inventor: Brian Donald Gerson