Patents by Inventor Brian Doyie

Brian Doyie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonplanar device with stress incorporation layer and method of fabrication
    Publication number: 20060261411
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
    Type: Application
    Filed: July 25, 2006
    Publication date: November 23, 2006
    Inventors: Scott Hareland, Robert Chau, Brian Doyie, Suman Datta, Been-Yih Jin