Abstract: A MOSFET includes a double silicided source/drain structure wherein the source/drain terminals include a silicided source/drain extension, a deep silicided source/drain region, and a doped semiconductor portion that surrounds a portion of the source/drain structure such that the silicides are isolated from the MOSFET body node. In a further aspect of the present invention, a barrier layer is formed around a gate electrode to prevent electrical shorts between a silicided source/drain extension and the gate electrode. A deep source/drain is then formed, self-aligned to sidewall spacers that are formed subsequent to the silicidation of the source/drain extension.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: A method and apparatus for capacitively coupling the input and output terminals of two semiconductor devices.

Abstract: A method and apparatus for capacitively coupling the input and output terminals of two semiconductor devices.

Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Abstract: A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system.

Abstract: A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.

Abstract: A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

Abstract: A MOSFET having a low resistance gate electrode structure includes silicided source and drain regions, and a silicided gate electrode wherein the thickness of the silicide layer superjacent the gate electrode is substantially thicker than the silicide layers overlying the source and drain regions.A process in accordance with the present invention decouples the silicidation of MOSFET source/drain regions from the silicidation of the gate electrode.

Abstract: A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: A CMOS device is provided having a high concentration of nitrogen atoms at the SiO.sub.2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices. In one embodiment, the process for providing the CMOS device resistant to hot carrier effects makes use of a sacrificial oxide layer through which the nitrogen atoms are implanted and is then removed. Following removal of the sacrificial oxide layer, a gate oxide is grown giving a CMOS device having high nitrogen concentration at the SiO.sub.2 /Si interface. In an alternate embodiment, nitrogen atoms are implanted through the final gate oxide using an implantation energy which does not damage the oxide layer.

Abstract: The invention enables precise and reliable adjustment of the resistance of a resistor formed in a zone (16) of monocrystalline semiconductor material (11) in spite of the presence of a density gradient of electrically active ions at the periphery of the zone, as a result of the implantation of ions of rare gases (+) in the zone. Furthermore, when the standard method of producing a resistor in a polycrystalline semiconductor material is used, implanting rare gas ions in the resistive zone enables precise and reliable adjustment of the resistance. The invention also maintains the dimensions of the initially resistive zone, despite later annealing, and is suitable for large-scale integration of circuits.

Abstract: A method for memorizing a data bit in an integrated static MOS-type RAM, a transistor for performing the method, and a memory produced by the method are described. An MOS transistor with a weakly doped channel has a hysteresis phenomenon with subthreshold conduction. The transistor is advantageously used as a memory element in an integrated static RAM cell.