Abstract: Method and apparatus for authenticating analog mixed-signal integrated circuits using process-specific functions (PSF) comprising: presenting wafer having plurality of dies, each die having circuit with identical design but having inherent physical differences due to process variation in their manufacture, each circuit designed to enhance the effects of the inherent differences; defining selected number of inputs/stimuli for authenticating and identifying each integrated circuit; defining expected response for each circuit, wherein the expected response for each circuit is the same due to the identical design; defining statistical window for analog response by the circuit to the inputs/stimuli; applying the inputs/stimuli to each circuit; receiving analog response corresponding to the applied inputs/stimuli, wherein the analog response falls outside statistical window when there are functional or physical changes to the circuit; separating from plurality of dies each die providing a response outside the stati

Abstract: A frequency-agile phase modulator with glitch-free multiplexer in CMOS process technologies for applications including wireless communications, radar, automotive radar, etc. Examples herein offer a novel phase modulator architecture that, when combined with either a wideband power amplifier or multiple narrowband amplifiers, allows for a single transmitter to transmit radar, communication, telemetry, or other similar waveforms across multiple frequency bands. The embodiments herein allow one transmitter to cover a very large operating frequency range, resulting in a decrease in size, weight, power consumption, and cost for future “small” platform systems. In an embodiment, the phase modulator circuit includes a reconfigurable delay-locked loop (DLL) circuit that is configured to receive a radio frequency (RF) input signal (RFin) and a configuration signal.

Abstract: A Low Voltage Differential Signaling (LVDS) compliant receiver includes a differential amplifier having inputs and outputs. A first input coupling capacitor and second input coupling capacitor are electrically coupled to each of the first differential input and the second differential input, respectively. The receiver also includes a first and a second regenerative feedback latching mechanism, and the first regenerative feedback latching mechanism is electrically coupled between the first input coupling capacitor and the first differential output. The second regenerative feedback latching mechanism is electrically coupled between the second input coupling capacitor and the second differential output.

Abstract: An interleaved digital to analog converter (DAC) includes at least a first signal path and a second signal path. The DAC further includes at least a first high speed DAC and a second high speed DAC each having an input and an output. The first signal path and the second signal path are electrically coupled to the first high speed DAC input and the second high speed DAC input, respectively. The DAC also includes a zero phase clock signal supplied to the first high speed DAC and a 180° phase shifted clock signal supplied to the second high speed DAC. A summation circuit, having at least two inputs and one output, is coupled to the outputs of the first high speed DAC and the second high speed DACs. A high-pass delta sigma modulator, a low-pass delta sigma modulator, a band pass delta sigma modulator, or notch filter delta sigma modulator is coupled between the first signal path and the first high speed DAC.