Abstract: A turn-oriented thread and/or process synchronization facility obtains a ticket value from a monotonically increasing ticket counter and waits until a memory location contains a value equal to the ticket value, yielding the processor between polls of the memory location only if a difference between the ticket value and the contents of the memory location exceeds a threshold value. Machine-readable media containing instructions to implement similar methods, and systems that can use the methods, are also described and claimed.

Abstract: The present application describes techniques for determining maximum acceptable modeled load latency (e.g., a model number of clock cycles required between the time a load issues and the time its use can issue) for instruction scheduling which uses less compile time, on the order of log2 (Maximum load latency—Minimum load latency). Typically, during instruction scheduling, register pressure is monotonically non-decreasing with respect to the scheduled load latency. Therefore, in some embodiments, a hierarchical search method is used to determine the acceptable schedule with the largest modeled load latency. According to an embodiment, a binary search is employed which reduces the compile time required to determine maximum load latency for which registers can be assigned.

Abstract: A turn-oriented thread and/or process synchronization facility obtains a ticket value from a monotonically increasing ticket counter and waits until a memory location contains a value equal to the ticket value, yielding the processor between polls of the memory location only if a difference between the ticket value and the contents of the memory location exceeds a threshold value. Machine-readable media containing instructions to implement similar methods, and systems that can use the methods, are also described and claimed.

Abstract: The present application, describes techniques for determining maximum acceptable modeled load latency (e.g., model number of clock cycle required between the time a load issues and the time its use can issue) for instruction scheduling which uses less compile time, in the order of log2 (Maximum load latency—Minimum load latency). Typically, during instruction scheduling, register pressure is monotonically non-decreasing with respect to the scheduled load latency. Therefore, in some embodiments, a hierarchical search method is used to determine the acceptable schedule with the largest modeled load latency. According to an embodiment, a binary search is employed which reduces the compile time required to determine maximum load latency for which registers can be assigned.

Abstract: Disclosed herein is an instruction set scheduling system for scheduling instruction sets in a pipelined processing system. In particular, the scheduling system includes a binary search technique for ascertaining the minimum acceptable iteration interval amongst a range of possible iteration intervals for use by the modulo scheduler.