Patents by Inventor Brian E. Burdick

Brian E. Burdick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Driving multiple consecutive bits in a serial data stream at multiple voltage levels
    Patent number: 7936829
    Abstract: Driving multiple consecutive bits having a same logic value in a serial data stream involves driving a first bit of the multiple consecutive bits in the serial data stream at an initial voltage level, and driving at least two additional bits of the multiple consecutive bits in the serial data stream at voltage levels stepped down from the initial voltage level.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 3, 2011
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Frederick G. Smith, Brian E. Burdick
  • Programmable transmit SCSI equalization
    Patent number: 6931560
    Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: August 16, 2005
    Assignee: LSI Logic Corporation
    Inventors: Edson W. Porter, Brian E. Burdick, Todd A. Randazzo, Kevin J. Bruno, Stephen R. Burnham, William K. Petty
  • Five volt tolerant and fail safe input scheme using source follower configuration
    Patent number: 6771113
    Abstract: An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Matthew S. Von Thun, Brian E. Burdick, Edson W. Porter
  • Multi-phase edge rate control for SCSI LVD
    Patent number: 6661271
    Abstract: An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 9, 2003
    Assignee: LSI Logic Corporation
    Inventors: Brian E. Burdick, Matthew S. Von Thun
  • MULTI-PHASE EDGE RATE CONTROL FOR SCSI LVD
    Publication number: 20030222689
    Abstract: An apparatus comprising a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Applicant: LSI LOGIC CORPORATION
    Inventors: Brian E. Burdick, Matthew S. Von Thun
  • High speed input
    Publication number: 20030042943
    Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 6, 2003
    Applicant: LSI Logic Corporation
    Inventors: Todd A. Randazzo, Brian E. Burdick, Edson W. Porter
  • High speed input buffer circuit
    Patent number: 6501318
    Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: December 31, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd A. Randazzo, Brian E. Burdick, Edson W. Porter