Abstract: A dedicated hardware CRC computation engine is provided to assure the integrity of data transferred between the system memory and storage devices. The CRC computation engine provides CRC calculation “on-the-fly” for the protection of data transferred to and from the system memory without software overhead. The computation of CRC values and optional checking against previously calculated CRC values is selected through the use of an address-mapping scheme. This CRC protection scheme requires a small amount of initial software overhead to allocate the data, CRC value, and CRC error regions of the system memory. After the CRC protection scheme is initialized, all CRC operations are transparent to the executing software.

Abstract: A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from system memory to CRC value cache memory all CRC values for all sub-blocks of a data block in response to access to a first CRC value for a first sub-block. This reduces overhead processing to arbitrate for control of the system memory for each CRC value for each sub-block of a block. The invention additionally provides that a separate cache table is maintained corresponding to each device within the storage controller that requests CRC values. Each of the multiple cache entry tables is therefore shorter and more rapidly searched as compared to prior techniques thereby further reducing overhead processing to manage the cached CRC values.

Abstract: Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache memory. The invention provides for circuits and methods for monitoring normal system accesses to system memory to manipulate CRC values in system memory in conjunction with associated access to disk drive of a storage subsystem. When accesses are detected loading or retrieving CRC values from system memory, the CRC values are loaded substantially in parallel into the CRC value cache memory.

Abstract: Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache memory. The invention provides for circuits and methods for monitoring normal system accesses to system memory to manipulate CRC values in system memory in conjunction with associated access to disk drive of a storage subsystem. When accesses are detected loading or retrieving CRC values from system memory, the CRC values are loaded substantially in parallel into the CRC value cache memory. This “fly-by” structure and method obviates the need for a separate, second access to system memory to load the accessed CRC values into the CRC value cache memory. Eliminating the second access to system memory reduced memory cycles on the system memory and arbitration for control thereof thus improving overall system performance.

Abstract: A bus bridge circuit having an internal loopback capability involving a shared memory interface integrated therewith. The bridge circuit of the present invention includes a primary PCI interface, a secondary PCI interface, and a shared memory interface. Transfer between the primary and secondary interfaces may proceed in parallel with transfers between the secondary interface and the shared memory interface. A single master device on the primary bus may perform loopback testing of the bridge circuit by directing downstream transactions between the primary interface and the shared memory interface via the secondary interface. Configuration parameters of the bridge circuit permit the address range of the shared memory interface to temporarily overlap the address range of the secondary interface. The primary bus master device configures such an overlapping range and directs transactions to the secondary interface in the overlapping address range.

Abstract: A bus bridge circuit having at least one register to store address ranges to enable or disable prefetch in upstream memory read transactions or upstream write transaction buffering/posting data to specific devices. The use of address ranges allows the present invention to provide selectable control of prefetch for upstream memory read transaction flow. This feature allows the continued use of read prefetch for targets that allow upstream read prefetch while disabling upstream read prefetch for targets that do not allow upstream read prefetch. Additionally, the use of the address range allows upstream memory write transaction flow without utilizing data buffering or posting for specific targets. This feature provides immediate delivery of upstream data to selected targets by selectively disabling buffering/posting of upstream memory write commands as performed by a FIFO buffer.

Abstract: A bus bridge circuit having a memory port integrated therewith for upstream memory access independent of the activity on the primary bus connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to an attached cache memory subsystem. The memory port of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port of the present invention utilizes FIFO devices to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus, while minimizing the performance impact on the secondary bus.