Patents by Inventor Brian E. Goodllin

Brian E. Goodllin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for reducing line edge roughness for conductive features
    Patent number: 7687407
    Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (?1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (?2).
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: March 30, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: David G. Farber, Brian E. Goodllin, Robert Kraft