Abstract: A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list.

Abstract: A method for processing commands includes receiving, for multiple commands, doorbells for writing to a send queue scheduler buffer on a host channel adapter (HCA). The send queue scheduler buffer is associated with a send queue scheduler. The method further includes detecting a potential deadlock of the send queue scheduler from processing a portion of the doorbells, writing a subset of the doorbells to a doorbell overflow buffer on a host, operatively connected to the HCA, based on detecting the potential deadlock, and discarding the subset by the send queue scheduler without processing the subset of the plurality of doorbells before discarding.

Abstract: A method for optimizing completion building is disclosed. The method involves receiving a work request by a host channel adapter (HCA), caching a portion of the work request in a completion cache in the HCA, wherein the cached portion of the work request includes information for building a completion for the work request, receiving, by the HCA, a response to the work request, querying the completion cache upon receiving the response to the work request to obtain the cached portion of the work request, and building the completion for the work request using the cached portion of the work request, wherein the completion informs a software application of at least a status of the work request as executed by the HCA.

Abstract: A method for debugging network activity involving receiving, by HCA, a packet stream comprising multiple packets, comparing a packet header of each of the packets to a trigger condition to determine whether the trigger condition has been met, after the trigger condition has been met, comparing each packet header of the packets to one or more trace filters stored in the HCA to identify matching packets, duplicating one or more portions of the matching packets and storing the duplicated portions of the matching packets in a trace buffer, where the trace buffer is located in the HCA and is dynamically repurposed from a payload RAM to the trace buffer when a corresponding port of the HCA for transmitting or receiving the packet stream is set to trace mode, and stopping the trace and copying the one or more portions of packets from the trace buffer to host memory.

Abstract: A method for deallocation of a memory region involving transmitting, by a host channel adapter (HCA), a first invalidation command for invalidating at least one key associated with the memory region, transmitting, by the HCA, a second invalidation command for invalidating a translation lookaside buffer (TLB) entry for the memory region, invalidate the at least one key associated with the memory region, determining whether all memory access requests to the memory region have been processed by the HCA, stalling processing of the second invalidation command when outstanding memory access requests to the memory region are present, and processing the outstanding memory access requests for the memory region by the HCA before executing the second invalidation command invalidating the TLB entry for the memory region.

Abstract: A method for managing a queue descriptor cache of a host channel adaptor (HCA) includes obtaining a queue descriptor from memory. The queue descriptor includes data describing a queue and the memory is located in a host system. The method further includes storing a copy of the queue descriptor in the queue descriptor cache of the HCA. The HCA accesses the copy of the queue descriptor to obtain the plurality of data, accesses the queue using the data, and updates the data to reflect the access to the queue. The method further includes calculating, using the data, a value corresponding to utilization of the queue, comparing the value against a threshold, fetching, if the value exceeds the threshold, a new copy of the queue descriptor from memory, and replacing the copy of the queue descriptor in the queue descriptor cache with the new copy obtained from the memory.

Abstract: A method for offloading includes a host channel adapter (HCA) receiving a first work request identifying a queue pair (QP), making a first determination that the QP is a proxy QP, and offloading the first work request to a proxy central processing unit (CPU) based on the first determination and based on the first work request satisfying a filter criterion. The HCA further receives a second work request identifying the QP, processes the second work request without offloading based on the QP being a proxy QP and based on the first work request failing to satisfy the filter criterion. The HCA redirects a first completion for the first work request and a second completion for the second work request to the proxy CPU based on the first determination. The proxy CPU processes the first completion and the second completion in order.

Abstract: A method for managing a distributed cache of a host channel adapter (HCA) that includes receiving a work request including a QP number, determining that a QP state identified by the QP number is not in the distributed cache, retrieving the QP state from main memory, and identifying a first portion and a second portion of the QP state. The method further includes storing the first portion into a first entry of a first sub-cache block associated with the first module, where the first entry is identified by a QP index number, storing the second portion into a second entry of a second sub-cache block associated with the second module, where the second entry is identified by the QP index number; and returning the QP index number of the QP state to the first module and the second module.

Abstract: A method for multicast replication by a host channel adapter (HCA) involving receiving a multicast packet, by a receive pipeline for processing packets of the HCA, storing, in a payload RAM within the HCA, a multicast packet payload corresponding to a data portion of the multicast packet, identifying, from a multicast header of the multicast packet, a plurality of destination underlying functions and a plurality of corresponding destination QPs to which the multicast packet is directed, wherein each destination underlying function of corresponds to a virtual machine located on a host, identifying, from the multicast header, information to be replicated for each multicast packet destination, injecting, by the HCA, a number of multicast packet descriptors corresponding to a number of the corresponding destination QPs into the receive pipeline of the HCA, and copying, from the payload RAM, the multicast packet payload to each of the corresponding destination QPs.

Abstract: A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network.

Abstract: A method for allocating resources of a host channel adapter includes the host channel adapter identifying an underlying function referenced in the first resource allocation request received from a virtual machine manager, determining that the first resource allocation request specifies a number of physical collect buffers (PCBs) allocated to the underlying function, allocating the number of PCBs to the underlying function, determining that the first resource allocation request specifies a number of virtual collect buffers (VCBs) allocated to the underlying function, and allocating the number of VCBs to the underlying function. The host channel adapter further receives command data for a command from the single virtual machine, determines that the underlying function has in use at least the number of PCBs when the command data is received, and drops the command data in the first command based on the underlying function having in use at least the number of PCBs.

Abstract: A method for allocating resources of a host channel adapter includes the host channel adapter identifying an underlying function referenced in the first resource allocation request received from a virtual machine manager, determining that the first resource allocation request specifies a number of physical collect buffers (PCBs) allocated to the underlying function, allocating the number of PCBs to the underlying function, determining that the first resource allocation request specifies a number of virtual collect buffers (VCBs) allocated to the underlying function, and allocating the number of VCBs to the underlying function. The host channel adapter further receives command data for a command from the single virtual machine, determines that the underlying function has in use at least the number of PCBs when the command data is received, and drops the command data in the first command based on the underlying function having in use at least the number of PCBs.

Abstract: A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list.

Abstract: A method for processing commands on a host channel adapter includes a host channel adapter receiving data from a host connected to the host channel adapter. The command includes an instruction, identification of packet data, and a length field. The host channel adapter extracts a length of the command from the length field, generates a scoreboard mask based on the length, where the scoreboard mask includes unused bits in the scoreboard preset, and sets, with each portion of the data received, a corresponding bit in a scoreboard. The host channel adapter further determines that the size of the data received for the command matches the length using the scoreboard, issues a kick on the host channel adapter when a size of the data received for the command matches the length, executes, in response to the kick, the instruction on a pipeline, and sends the packet data on a network.

Abstract: A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.

Abstract: An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the transaction buffers where additional capacity is required by that transaction buffer.

Abstract: An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.

Abstract: An interconnect apparatus provides for the buffering of information among a plurality of retry buffers in an output port. An additional buffer is dynamically assignable to one of the N retry buffer means where additional capacity is required by that retry buffer.