Patents by Inventor Brian Eugene Curcio

Brian Eugene Curcio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for filling high aspect ratio via holes in electronic substrates
    Patent number: 6581280
    Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: June 24, 2003
    Assignee: International Business Machines Corporation
    Inventors: Brian Eugene Curcio, Peter Alfred Gruber, Frederic Maurer, Konstantinos I. Papathomas, Mark David Poliks
  • Structure for high speed printed wiring boards with multiple differential impedance-controlled layer
    Patent number: 6570102
    Abstract: A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas Richard Miller, Konstantinos I. Papathomas, Brian Eugene Curcio, Joseph J. Sniezek
  • Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
    Publication number: 20020179335
    Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.
    Type: Application
    Filed: July 17, 2002
    Publication date: December 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: Brian Eugene Curcio, Peter Alfred Gruber, Frederic Maurer, Konstantinos I. Papathomas, Mark David Poliks
  • Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
    Patent number: 6452117
    Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Brian Eugene Curcio, Peter Alfred Gruber, Frederic Maurer, Konstantinos I. Papathomas, Mark David Poliks
  • Structure for high speed printed wiring boards with multiple differential impedance-controlled layer
    Publication number: 20020007966
    Abstract: A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.
    Type: Application
    Filed: June 11, 2001
    Publication date: January 24, 2002
    Applicant: International Business Machines Corporation
    Inventors: Thomas Richard Miller, Konstantinos I. Papathomas, Brian Eugene Curcio, Joseph J. Sniezek