Abstract: Systems and methods for reducing power consumption during data transport across multiple processors when link utilization is low. In a multi-node system, at least one of two nodes may indicate low utilization for a given link between them. In response to further determining no enabled link between the two nodes is over utilized, each of the two nodes may remove the given link from consideration for being scheduled to receive data for transfer and turn off the given link when no more transactions are scheduled for the given link. Disabled links may be re-enabled when high utilization is detected on at least one link between the two nodes.

Abstract: Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path.

Abstract: Systems and methods for reducing power consumption during data transport across multiple processors when link utilization is low. In a multi-node system, at least one of two nodes may indicate low utilization for a given link between them. In response to further determining no enabled link between the two nodes is over utilized, each of the two nodes may remove the given link from consideration for being scheduled to receive data for transfer and turn off the given link when no more transactions are scheduled for the given link. Disabled links may be re-enabled when high utilization is detected on at least one link between the two nodes.

Abstract: In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to generate an index to the branch prediction array responsive to at least a portion of a fetch address corresponding to a fetch request that is at a first pipeline stage of the processor and further responsive to a branch history. The control unit is configured to update the branch history responsive to a first fetch request at the first pipeline stage and to defer the update for a second fetch request to a second pipeline stage subsequent to the first pipeline stage.

Abstract: A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the instructions to be requested, the latency involved in requesting instructions from higher levels of memory may be avoided. A pre-fetched line of instruction may be stored into a pre-fetch buffer residing on a microprocessor. The pre-fetch buffer may be used by the microprocessor as an alternate source from which to retrieve a requested instruction when the requested instruction is not stored within the first level cache. The particular line of instruction being pre-fetched may be identified based on a configurable stride value. The configurable stride value may be adjusted to maximize the likelihood that a requested instruction, not present in the first level cache, is present in the pre-fetch buffer. The configurable stride value may be updated manually or automatically.

Abstract: A boundary scan cell including a three-state output buffer, a test data scan flip-flop for providing an input to the three-state buffer, a control data scan flip-flop for receiving a serial control data input, independent clock signals for independently clocking the test data scan flip-flop and the control data scan flip-flop, and control circuitry for controllably providing the output of the control data scan flip-flop to the three-state output driver such that the enabled state of the three-state output buffer is controlled by the output of the control data scan flip-flop, whereby the enabled state of the three-state output driver is controlled independently of the test data in the test data scan flip-flop.

Abstract: Boundary scan cells including mask circuitry having a mask latch for storing a mask flag that is serially scanned into the cell via a scan flip-flop. In a boundary scan cell having an output function, control circuitry responsive to the mask flag forces or holds the output of the cell at a state determined by one or more values scanned into the cell via the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked. In a boundary scan cell having an input function, control circuitry responsive to the mask flag connects the output of the scan flip-flop to the input of the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked.