Abstract: A stepper motor driver system includes: a digital signal controller configured to digitally synthesize synthesized analog voltage signals that will induce a desired velocity of a stepper motor when applied to a pair of stepper motor windings; and voltage amplifiers, communicatively coupled to the digital signal controller, configured to amplify the synthesized analog voltage signals to produce amplified analog voltage signals and to output the amplified analog voltage signals; where the digital signal controller is configured to synthesize the analog voltage signals by affecting at least one of a phase or an amplitude of each of the analog voltage signals as a function of the desired velocity of the stepper motor.

Abstract: A stepper motor driver system includes: a digital signal controller configured to digitally synthesize synthesized analog voltage signals that will induce a desired velocity of a stepper motor when applied to a pair of stepper motor windings; and voltage amplifiers, communicatively coupled to the digital signal controller, configured to amplify the synthesized analog voltage signals to produce amplified analog voltage signals and to output the amplified analog voltage signals; where the digital signal controller is configured to synthesize the analog voltage signals by affecting at least one of a phase or an amplitude of each of the analog voltage signals as a function of the desired velocity of the stepper motor

Abstract: A local clock system for generating a local clock signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, wherein the output local clock signal is a non-integer multiple of the input clock reference signal. A numerically controlled generator generates the clock output signal, and the frequency and phase thereof are controlled by a digital tuning word input thereto. An input frequency divider divides the input clock reference signal by a first constant k.sub.11 or a second constant k.sub.22, and an output frequency divider for dividing the output signal by a first constant k.sub.11 or a second constant k.sub.21. A relay-phase detector receives output signals from the input frequency divider and the output frequency divider, and produces a 0 or a 1 output, which controls the input frequency divider to divide by k.sub.12 or k.sub.22 and controls the output frequency divider to divide by k.sub.11 or k.sub.

Abstract: A local clock system uses a numerically controlled oscillator referenced to a stable oscillator to generate local clock signals under microprocessor control. Two feedback loops provide inputs to the microprocessor for maintaining synchronization with the external clock reference; a frequency locked and a phase-locked loop. The relatively wide-band frequency-locked loop is used to acquire initial synchronization with the external clock reference when the external clock is restored after having been lost or is switched to a new source. The phase-locked loop has a narrow bandwidth and provides a large attenuation of any jitter on the incoming reference with a resultant low output jitter. The microprocessor provides a hold-over operation upon loss of the external clock reference and when the external reference is restored it slowly adjusts the output clock frequency to match that of the reference, limiting the rate of adjustment so as not to exceed a specified allowable jitter in the local clock output.

Abstract: A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling numerically controlled oscillator and clock circuit which provide a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. Pointer adjustments are processed separately from the SONET SPE payload frequency tracking. That is, the processing of pointers, which indicates a change in the phase of the SONET SPE payload, includes detecting negative or positive pointer hits by monitoring, for example, the H1, H2 bytes in the transport overhead, and advancing or retarding the phase over a predetermined period of time.

Abstract: A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling either a direct digital synthesis circuit that provides a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. To minimize jitter and buffer spills (i.e., data overruns or underruns), the frequency and phase of the desynchronized clock is constantly varied to match the variations of the data rate of incoming SONET data. The DDS circuit generates the desynchronized clock, which has a center frequency equal to a predetermined frequency of a reference clock, whose phase is advanced or retarded in accordance with the magnitude of a tuning word supplied by a controller, which implements either a linear, non-linear, or fuzzy logic control algorithm.