Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract: A filter assembly is provided which includes an outer filter sleeve formed at least in part by a plurality of pleats, an inner filter sleeve formed at least in part by a plurality of pleats, wherein the inner and outer filter sleeves define a passage therebetween. An inlet cap is secured to a first end of the inner and outer filter sleeves and it has at least one inlet port communicating with the passage, and an end cap is secured to a second end of the inner and outer filter sleeves and it has an end surface closing the passage. Methods of forming such a filter assembly are also provided.

Abstract: A filter assembly is provided which includes an outer filter sleeve formed at least in part by a plurality of pleats, an inner filter sleeve formed at least in part by a plurality of pleats, wherein the inner and outer filter sleeves define a passage therebetween. An inlet cap is secured to a first end of the inner and outer filter sleeves and it has at least one inlet port communicating with the passage, and an end cap is secured to a second end of the inner and outer filter sleeves and it has an end surface closing the passage. Methods of forming such a filter assembly are also provided.

Abstract: An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another subset of the instructions can be utilized by the digital signal processor. A software application can thus take advantage of digital signal processing capabilities in the same program, obviating the need for separate programs for separate processors.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices.