Abstract: A missile guidance method that applies a curvature parameterization to a line-of-sight unit vector between a missile and a target. A line-of-sight rotation rate is derived from the line-of-sight unit vector with the applied curvature parameterization. In some embodiments, the curvature parameterization is learned by a deep learning network (e.g., a deep neural network that includes a recurrent layer). The deep neural network may be optimized using meta reinforcement learning over an ensemble of engagement scenarios with varying target behavior.

Abstract: A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during a first system clock cycle, where Q<P, and sends, during the first system clock cycle, the Q data units to a processing device configured to process a maximum of Q data units per system clock cycle.

Abstract: A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.

Abstract: A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during a first system clock cycle, where Q<P, and sends, during the first system clock cycle, the Q data units to a processing device configured to process a maximum of Q data units per system clock cycle.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.

Abstract: A packet processing system converts a wide bus carrying P packets to a narrower bus that can carry only Q packets, where Q<P. The packet processing system includes a first data path, a queue, a shift register and a control unit. The first data path receives up to P packets during a first processing cycle. The queue stores the P packets in a queue. The control unit shifts a first quantity of data of the P packets into the shift register from the queue and selectively retrieves data from the shift register until a first packet of the plurality of packets is retrieved. The control unit then sends the first packet on a second data path during the first processing cycle.

Abstract: A pipelined escape character insertion component sequentially includes a character specific gap inserter and an expansion component. The gap inserter inserts gaps into blocks of data in a received data stream in which data elements within the blocks correspond to control elements. The expansion component receives the blocks of data elements with the inserted gaps and rearranges the gaps to positions adjacent to the data elements that correspond to the control elements. Additionally, an escape character follows the expansion component and inserts escape characters in the inserted gaps.

Abstract: A system for removing gaps from streams of packets is provided. The system includes a packet splitter, a header buffer, a data buffer, and a packet combiner. The packet splitter receives the packets. Each of the packets includes a packet header and packet data. The packet splitter separates the packet header from the packet data for each of the packets. The header buffer stores the packet headers and the data buffer stores the packet data. The packet combiner reassembles the packets from the packet headers in the header buffer and the packet data in the data buffer and removes gaps from the reassembled packets.

Abstract: A high-speed network switch includes a data bus for transmitting data between devices. The data bus includes a plurality of data lines and a clock line. As packet data is received by the high-speed network switch, the packet data is divided into byte-wide cells for transmission over the data lines. While the cells are transmitted over the data lines, a half-speed clock is transmitted over the clock line. Transitions in the half-speed clock occur during transmission of the cell data. The transitions are used by a receiving device to sample the byte-wide cells.

Abstract: A network switch divides incoming frame data into cells. Each of the cells include a source identification field. Depending upon bandwidth availability and upon cell priority, the cells are transmitted over a switch bus. The cells are then routed based upon the source identification field. The network switch determines bandwidth usage by monitoring the switch bus. Upon detection of a start-of-frame cell, the network switch increments a bandwidth counter. Upon detection of an end-of-frame cell, the network switch adds an entry to a decrement FIFO. After a switch bus latency period, the network switch removes the entry from the decrement FIFO and decrements the bandwidth counter.

Abstract: A clock recovery architecture for recovering clock and serial data from an incoming data stream of a local area network station. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. A single clock generation module (CGM) and N phase multiplexers, one for each clock recovery channel on a chip, is used to select one of M phases of a 250 Mhz clock signal from the CGM for each clock recovery channel. To provide the required phase resolution, a phase interpolator is used. The phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer. Each phase multiplexer is advanced or retarded in response to the pump-up (pumpup) or pump-down (pumpdn) signals from each clock recovery channel (CRM).

Abstract: A circuit for reducing the ground and power supply bounce of the output drivers in a group of I/O cells. A replica I/O cell is part of a delay locked loop which uses closed-loop feedback control to determine the magnitude of a bias current needed to cause the delay through the replica cell to be equal to a reference value. By forcing the delay through the replica cell to be equal to a desired reference value, the magnitude of bias current required to control the delay through each of the I/O cells in an I/O ring so that the delay approaches the reference value can be determined. As a result, by properly selecting the reference delay value, the magnitude of the bias current required to compensate for delay variations arising from multiple sources (e.g., PVT) can be determined. Since this reduces the rate of change of the current in the output drivers of the actual I/O cells, the induced voltage responsible for the ground and/or power supply bounce in those cells is reduced.

Abstract: A programmable phase adjuster spans a clock signal's period with N linearly distributed phase steps. The resulting phase adjust resolution is finer than that of an inverter delay for a given process. Enhancement of the phase resolution of a phase picker CRM architecture enables use of the architecture for recovering clock signals from high data rate data streams in a way that minimizes power and area and allows optimization for multi-channel applications.

Abstract: A programmable phase adjuster spans a clock signal's period with N linearly distributed phase steps. The resulting phase adjust resolution is finer than that of an inverter delay for a given process. Enhancement of the phase resolution of a phase picker CRM architecture enables use of the architecture for recovering clock signals from high data rate data streams in a way that minimizes power and area and allows optimization for multi-channel applications.

Abstract: An apparatus for and method of removing duty cycle distortion jitter from data by adaptive equalization are disclosed. The apparatus includes an equalization circuit which equalizes input data based on an equalization control signal, a signal analysis circuit, and a control circuit which generates the equalization control signal. A multiport apparatus includes a plurality of equalization circuits, a multiplexor, a signal analysis circuit, and a control circuit. A method includes the steps of receiving an equalization control signal and the input data signal, equalizing the input data signal based on the equalization control signal, analyzing the equalized data signal and generating an analysis result signal, and generating the equalization control signal based on the analysis result signal.