Abstract: Configuration-adjusting mechanisms include linkages interconnecting first and second layers of a sheet material. The linkages have hinges positioned and oriented to cause motion of at least a portion of the linkages out of a plane of the first and second layers when the mechanisms are actuated. An apparatus, system, and method include one or more of the mechanisms for changing a contour of a surface provided by a cover overlying the mechanisms. An array of mechanisms or mechanisms corresponding to an array of positions on the surface may be selectively actuated to change the contour or texture of the surface. The array of mechanisms for changing the contour can provide user interface buttons selectively actuated by the mechanisms, which cause the buttons to emerge from the surface. A reconfigurable contour may be provided by selectable sets of the buttons associated with respective functions of a control panel, for example.

Abstract: A method and apparatus for performing pipelined computations that include cross-iteration computations. The apparatus includes a functional unit having at least one input and an output, each input being operable to receive an input data value and an associated input data validity tag indicative of the validity of the input data value and the output being operable to provide an output data value and an associated output data validity tag indicative of the validity of the output data value. The first functional unit is operable in a first mode in which an output data value from the first functional unit is valid if all of the input data values are valid, and in a second mode in which the output data value from the first functional unit is valid if any of the input data values is valid.

Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Abstract: A motor control for a reciprocating load includes overvoltage suppression. The motor control comprises a variable frequency drive (VFD) operatively connected to a power source for operating a motor to drive the reciprocating load. A sensor determines motor torque. A control unit is connected to the VFD and to the sensor and is adapted to control the VFD in a normal mode to operate the motor at a select reference frequency. The control unit predicts occurrence of a negative motor torque condition based on sensed motor torque and in response to a negative motor torque condition controls the VFD in a negative motor torque mode to operate the motor at a higher frequency than the select reference frequency to prevent the motor from entering a negative slip condition.

Abstract: A motor control for a reciprocating load includes overvoltage suppression. The motor control comprises a variable frequency drive (VFD) operatively connected to a power source for operating a motor to drive the reciprocating load. A sensor determines motor torque. A control unit is connected to the VFD and to the sensor and is adapted to control the VFD in a normal mode to operate the motor at a select reference frequency. The control unit predicts occurrence of a negative motor torque condition based on sensed motor torque and in response to a negative motor torque condition controls the VFD in a negative motor torque mode to operate the motor at a higher frequency than the select reference frequency to prevent the motor from entering a negative slip condition.

Abstract: A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model.

Abstract: A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Abstract: An interconnection device (300) with a number of links (306, 308, 310, 312 and 314), each link having a number of link input ports (302), link output ports (304) and storage registers (316). An input selection switch (402) is coupled to a selected link input port to receive an input data token. The storage registers (316) may be used to store input data tokens. A storage access switch (404) is coupled to the input selection switch (402) and to the storage registers (316) and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch (406) receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input (502, 522) of the data-flow graph, a computational instruction is generated for each node (506, 510, 514 etc) of the data-flow graph, and a sink instruction is generated for each output (520, 540) of the data-flow graph. The computation instruction for a node includes a descriptor of the operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list (A, B, C, . . . , J, K, L, FIG. 2) comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier.

Abstract: A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated (104) and the nodes are scheduled for throughput (106) by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle (110). The edges of the data-flow graph are allocated (122) to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Abstract: An interconnection device (300) with a number of links (306, 308, 310, 312 and 314), each link having a number of link input ports (302), link output ports (304) and storage registers (316). An input selection switch (402) is coupled to a selected link input port to receive an input data token. The storage registers (316) may be used to store input data tokens. A storage access switch (404) is coupled to the input selection switch (402) and to the storage registers (316) and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch (406) receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

Abstract: A memory interface device (100) providing a fractional address interface between a data processor (104) and a memory system (102) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator (108) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit (110) coupled to the address generator (108) for retrieving first and second data values from the memory system (102) at the first and second memory addresses, respectively. The device also includes a data access unit (112) for interpolating between the first and second data values and passing the interpolated value to the data processor (104).

Abstract: A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model.

Abstract: A compound library comprises a plurality of different units each comprising a solid support with which is associated a single member of the compound library, each solid support has a defined chemical composition which acts as an intrinsic label capable of identifying the first choice in the synthesis of the associated member of the compound library.

Abstract: A polymer support is provided which comprises hydroxypolyC2-4 alkyleneoxy chains attached to a cross-linked polymer. The hydroxypolyC2-4 alkyleneoxy chain contains from 2 to 8 C2-4 alkyleneoxy groups and the polymer support has from about 0.1 to about 5 meq free hydroxy groups per gram of polymer. Preferably, the cross linked polymer is a copolymer comprising phenylethylene and 4-hydroxyphenylethylene units or phenylethylene and 4-chloromethylphenylethylene units.

Abstract: A compound library comprises a plurality of different units each comprising a solid support with which is associated a single member of the compound library, each solid support has a defined chemical composition which acts as an intrinsic label capable of identifying the first reaction choice in the synthesis of the associated member of the compound library.

Abstract: A process for preparing agrochemical intermediates of formula (I), wherein W is (CH.sub.3 O).sub.2 CH.CHCO.sub.2 CH.sub.3 or CH.sub.3 O.CH.dbd.CCO.sub.2 CH.sub.3 ; Z.sup.1 is a halogen atom; and R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are independently hydrogen, halogen, C.sub.1-4 alky, C alkoxy, acetoxy or acyl; the process comprising the steps of: (a) reacting a compound of formula (II), wherein X, R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are as defined above, with a compound of formula ROCH.sub.3, wherein R is a metal; and, (b) reacting the product of (a) with a compound of formula (III), wherein Z.sup.1 and Z.sup.2 are halogen atoms. A process for the preparation of compounds of formula (II) and compounds of formula (II) themselves. A process for obtaining, in substantially pure form, a compound of formula (11) and compounds of formula (II) themselves. A process for obtaining, in substantially pure form, a compound of formula (11) wherein R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are all hydrogen.

Abstract: A process for making a 1,2-benzisothiazolin-3-one by cycling a bisamide precursor under alkaline conditions in the presence of oxygen or an oxygen-release compound in the presence of a nitrogen, sulphur or phosphorus nucelophile.

Abstract: The trimethylsulphonium salt of N-phosphonomethylglycine is prepared by reacting N-phosphonomethylglycine, preferably in the form of a solid, with an aqueous solution of trimethylsulphonium carbonate or trimethylsulphonium bicarbonate or a mixture thereof. The trimethylsulphonium carbonate or trimethylsulphonium bicarbonate may be prepared by bubbling carbon dioxide through an aqueous solution of trimethylsulphonium hydroxide. It is possible to manufacture trimethylsulphonium carbonate or bicarbonate at one site and then transport them to a different site for local manufacture of N-phosphonomethylglycine in a relatively unsophisticated plant which produces minimal effluent.